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公开(公告)号：US20100076536A1
公开(公告)日：2010-03-25
申请号：US12442133
申请日：2007-09-18
CPC分类号： A61N1/0529 , A61B5/04001 , A61L31/148 , A61N1/0531 , A61N1/0534 , A61N1/0536 , A61N1/0539 , A61N1/0558 , A61N1/36082
摘要： The invention provides an implantable multi-electrode device (300) and related methods and apparatuses. In one embodiment, the invention includes an implantable device (300) comprising: an assembly block (320); and a plurality of leads (340 . . . 348) radiating from the assembly block (320), each of the plurality of leads (340 . . . 348) containing at least one electrode (342A), such that the electrodes are distributed within a three-dimensional space, wherein the assembly block (320) includes a barb (350) for anchoring the assembly block (320) within implanted tissue.
摘要翻译： 本发明提供一种可植入式多电极装置（300）及其相关方法和装置。 在一个实施例中，本发明包括可植入装置（300），包括：组装块（320）; 以及从所述组装块（320）辐射的多个引线（340 ... 348），所述多个引线（340 ... 348）中的每一个包含至少一个电极（342A），使得所述电极分布在 三维空间，其中组装块（320）包括用于将组装块（320）固定在植入的组织内的倒钩（350）。
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公开(公告)号：US08798737B2
公开(公告)日：2014-08-05
申请号：US12442133
申请日：2007-09-18
IPC分类号： A61N1/00
CPC分类号： A61N1/0529 , A61B5/04001 , A61L31/148 , A61N1/0531 , A61N1/0534 , A61N1/0536 , A61N1/0539 , A61N1/0558 , A61N1/36082
摘要： The invention provides an implantable multi-electrode device (300) and related methods and apparatuses. In one embodiment, the invention includes an implantable device (300) comprising: an assembly block (320); and a plurality of leads (340 . . . 348) radiating from the assembly block (320), each of the plurality of leads (340 . . . 348) containing at least one electrode (342A), such that the electrodes are distributed within a three-dimensional space, wherein the assembly block (320) includes a barb (350) for anchoring the assembly block (320) within implanted tissue.
摘要翻译： 本发明提供一种可植入式多电极装置（300）及其相关方法和装置。 在一个实施例中，本发明包括可植入装置（300），包括：组装块（320）; 以及从所述组装块（320）辐射的多个引线（340 ... 348），所述多个引线（340 ... 348）中的每一个包含至少一个电极（342A），使得所述电极分布在 三维空间，其中组装块（320）包括用于将组装块（320）固定在植入的组织内的倒钩（350）。
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公开(公告)号：US20100066348A1
公开(公告)日：2010-03-18
申请号：US12595090
申请日：2008-04-05
CPC分类号： G01N33/48721 , C12Q1/6869 , G01N27/414 , C12Q2565/631
摘要： A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.
摘要翻译： 检测器装置包括衬底（50），源极区（S）和漏极区（D）以及在源极和漏极区之间的沟道区（65）。 纳米孔（54）穿过沟道区域，并且连接在衬底的相对侧上的流体室（56,58）。 在流体室，源极和漏极区之间提供电压偏置，并且感测源区和漏区之间的电荷流。 该装置使用纳米孔来限制待测样品（例如核苷酸）靠近传感器。 可以使传感器的尺寸与DNA链中相邻核苷酸的间隔相似。 以这种方式，避免了基于PCR的DNA测序技术的缺点，可以实现单核苷酸分辨率。
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公开(公告)号：US20100041988A1
公开(公告)日：2010-02-18
申请号：US12442197
申请日：2007-09-19
CPC分类号： A61B17/2202 , A61B17/2256 , A61B2017/00106
摘要： A method is disclosed using a feedback loop for focused ultrasound application. The method includes the steps of determining a location of a target side within a body using ultrasound waves, applying focused ultrasound waves to the target site, determining a new location of the target site using further ultrasound waves, and adjusting the focused ultrasound waves in response to the new location of the target site.
摘要翻译： 公开了一种使用聚焦超声应用的反馈回路的方法。 该方法包括以下步骤：使用超声波确定身体内目标侧的位置，向目标位置施加聚焦超声波，使用另外的超声波确定目标位置的新位置，以及响应于调整聚焦超声波 到目标网站的新位置。
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公开(公告)号：US09034637B2
公开(公告)日：2015-05-19
申请号：US12595090
申请日：2008-04-05
IPC分类号： C12M1/34 , C12M1/00 , C12M3/00 , G01R31/26 , H01L21/66 , G01N33/487 , C12Q1/68 , G01N27/414
CPC分类号： G01N33/48721 , C12Q1/6869 , G01N27/414 , C12Q2565/631
摘要： A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.
摘要翻译： 检测器装置包括衬底（50），源极区（S）和漏极区（D）以及在源极和漏极区之间的沟道区（65）。 纳米孔（54）穿过沟道区域，并且连接在衬底的相对侧上的流体室（56,58）。 在流体室，源极和漏极区之间提供电压偏置，并且感测源区和漏区之间的电荷流。 该装置使用纳米孔来限制待测样品（例如核苷酸）靠近传感器。 可以使传感器的尺寸与DNA链中相邻核苷酸的间隔相似。 以这种方式，避免了基于PCR的DNA测序技术的缺点，可以实现单核苷酸分辨率。
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公开(公告)号：US07488669B2
公开(公告)日：2009-02-10
申请号：US11083356
申请日：2005-03-16
IPC分类号： H01L21/46
CPC分类号： H01L27/0203 , H01L27/1203 , H01L29/78648
摘要： A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.
摘要翻译： 公开了一种在SOI晶片上制造用于双栅极SOI处理的至少一个标记（MX）的方法。 标记物在第一方向上具有衍射结构，并且衍射结构被配置为在使用期间在用于在第一方向上检测的对准和覆盖检测系统中产生非对称衍射图案。
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7.发明授权Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers 失效具有使用SiGe间隔物的具有LDD结构的MOS晶体管的半导体器件的制造公开(公告)号：US06255183B1
公开(公告)日：2001-07-03
申请号：US09064207
申请日：1998-04-22
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/28247 , H01L21/823864 , H01L29/665 , Y10S438/923
摘要： A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed. In the method, a layer of semiconductor material formed by Si1-xGex, 0.1
摘要翻译： 一种制造具有LDD结构的MOS晶体管的半导体器件的方法。 在硅衬底（1）的表面（5）上形成栅电介质（6）和栅电极（7,8）。 然后暴露与栅电极相邻的表面，并且在与栅电极相邻的表面的边缘（9）上形成一层半导体材料（10）。 随后，栅极电极和半导体材料层用作掩模，随后引入离子（13,14）。 最后，进行热处理，由此通过激活注入的离子并且通过从半导体材料层扩散掺杂剂的原子而形成源极区（16,17）和漏极区（18,19）。 这些由扩散形成的这些区域的部分（b）在这里是弱掺杂的，位于通过激活注入的离子和沟道区（20,21）形成的更强的掺杂部分（a）之间。 因此形成了LDD结构。 在该方法中，在与栅电极相邻的边缘上设置由Si1-xGex形成的半导体材料层，0.1
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8.发明授权Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel 有权在双栅极FET中制造自对准源极和漏极接触的方法，其中可控制造薄的Si或非Si沟道公开(公告)号：US07795112B2
公开(公告)日：2010-09-14
申请号：US11093265
申请日：2005-03-28
IPC分类号： H01L21/30
CPC分类号： B82Y10/00 , H01L21/26506 , H01L29/66575
摘要： A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.
摘要翻译： 公开了一种在衬底（SOI）上形成晶体管结构的方法，其中衬底包括支撑Si层，掩埋绝缘层和顶部Si层。 该方法包括在顶部Si层上形成晶体管结构的栅极区域，其中栅极区域通过介电层从顶部Si层分离，并且其中顶部Si层包括高掺杂剂水平。 该方法还包括在由分界氧化物和/或抗蚀剂层区域划定的顶部Si层上形成开放区域，通过离子注入形成高级杂质或严重损坏的区域，并将开放区域暴露于离子束，其中 离子束包括光束能量和剂量的组合，并且其中分界层区域和栅极区域用作注入掩模。
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9.发明申请公开(公告)号：US20080203476A1
公开(公告)日：2008-08-28
申请号：US11813015
申请日：2005-12-19
申请人： Youri V. Ponomarev
发明人： Youri V. Ponomarev
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L27/1266 , H01L29/42392 , H01L29/66795
摘要： The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a second conductivity type opposed to the first, and a drain region (5) of the first conductivity type are arranged in succession, successively, seen in the longitudinal direction of the strip-shaped semiconductor region (3,3A,3B), and wherein the channel region (33) is provided with a gate dielectric (6), on which a first gate electrode (7) is present on a first vertical side of the strip-shaped semiconductor region (3,3A,3B), which gate electrode (7) is provided with a first connection region (7A), and on which a second gate electrode (8) is present on a second vertical side of the strip-shaped semiconductor region (3,3A,3B) positioned opposite the first vertical side, which second gate electrode (8) is provided with a second connection region (8A). According to the invention the first and second gate electrodes (7,8) completely fill the space on either side of the strip-shaped semiconductor region (3,3A,3B) over the width of the connection regions (7A,8A). In a preferred embodiment the gate electrodes (7,8) each border a horizontal side of the strip-shaped semiconductor region (3,3A,3B). The device (10) according to the invention is very compact, suitable for the sub 45 nm domain and easy to manufacture.
摘要翻译： 本发明涉及由衬底（11）和半导体本体（2）构成的半导体器件（10），半导体器件（2）包括形成场效应晶体管的硅片的带状半导体区域（3,3A，3B） ，其中连续地依次排列第一导电类型的源极区（4），与第一导电类型相对的第二导电类型的沟道区（33）和第一导电类型的漏极区（5） 在条形半导体区域（3,3A，3B）的纵向方向上，并且其中沟道区域（33）设置有栅极电介质（6），其上存在第一栅电极（7） 在所述条形半导体区域（3,3A，3B）的第一垂直侧上，所述栅电极（7）设置有第一连接区域（7A），并且所述第二栅电极（8） 存在于位于对面的条形半导体区域（3,3A，3B）的第二垂直侧 位于第一垂直侧，该第二栅电极（8）设置有第二连接区域（8A）。 根据本发明，第一和第二栅电极（7,8）在连接区域（7A，8）的宽度上完全填充条形半导体区域（3,3A，3B）两侧的空间 一个）。 在优选实施例中，栅极电极（7,8）分别与条形半导体区域（3,3A，3B）的水平边界。 根据本发明的装置（10）非常紧凑，适合于低于45nm的结构域并且易于制造。
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