利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

70 条记录 (耗时 0.025 秒)

    Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics
    1.
    发明授权
    Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics 失效
    用于在层间电介质形成通孔和沟槽期间减少蚀刻损伤的技术

    公开(公告)号：US07309654B2

    公开(公告)日：2007-12-18

    申请号：US11380094

    申请日：2006-04-25

    申请人： Matthias Schaller ,  Massud Aminpur ,  James Werking

    发明人： Matthias Schaller ,  Massud Aminpur ,  James Werking

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31116 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808

    摘要： By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.

    摘要翻译： 通过执行用于在具有不同去除速率的金属化层中形成通孔开口和描绘沟槽或开口区域的第一常用蚀刻工艺，可以延迟描绘沟槽或开放区域中的蚀刻前沿，从而显着降低晶片电弧的可能性 。 随后，在另一常见的蚀刻工艺中，描绘沟槽或开放区域可以被蚀刻到相应的蚀刻停止层，在此期间在通孔开口上方形成沟槽。

    Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics
    3.
    发明授权
    Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics 有权
    在低k层间电介质形成通孔和沟槽期间增强工艺灵活性的技术

    公开(公告)号：US07763547B2

    公开(公告)日：2010-07-27

    申请号：US11199526

    申请日：2005-08-08

    申请人： Thomas Werner ,  Matthias Schaller ,  Massud Aminpur

    发明人： Thomas Werner ,  Matthias Schaller ,  Massud Aminpur

    IPC分类号： H01L21/3065 ,  H01L21/302

    CPC分类号： H01L21/31138 ,  H01L21/31116 ,  H01L21/76808 ,  H01L21/76834

    摘要： In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k dielectric in that the reduction in thickness is substantially achieved during the resist removal. For this purpose, the resist plasma etch may correspondingly be controlled to obtain the desired target thickness of the etch stop layer, wherein fluorine may be provided from an external source and/or fluorine may be generated in a controlled manner from polymer layers deposited within the etch chamber.

    摘要翻译： 在用于在低k电介质层中形成通孔开口和沟槽开口的蚀刻工艺中，下层蚀刻停止层的材料去除与通过低k电介质的蚀刻分离，因为厚度的减小在 抵抗力消除。 为此，可以相应地控制抗蚀剂等离子体蚀刻以获得蚀刻停止层的期望目标厚度，其中可以从外部源提供氟，和/或​​氟可以以受控的方式从沉积在 蚀刻室。

    Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches
    4.
    发明申请
    Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches 有权
    用于通过沟槽边缘四舍五入来增强电化学沉积过程中的填充能力的技术

    公开(公告)号：US20060046495A1

    公开(公告)日：2006-03-02

    申请号：US11122591

    申请日：2005-05-05

    申请人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur

    发明人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur

    IPC分类号： H01L21/461

    CPC分类号： H01L21/76804 ,  H01L21/7688

    摘要： During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.

    摘要翻译： 在低k电介质材料中形成金属线时，形成在封盖层中的沟槽的上部和低k电介质材料被处理以提供扩大的锥形或圆角圆化，从而显着提高填充能力 随后的金属沉积工艺。 在一个特定实施例中，在蚀刻通过覆盖层和低k电介质层之后并且在抗蚀剂移除之后执行附加蚀刻工艺。

    Technique for controlling mechanical stress in a channel region by spacer removal
    5.
    发明授权
    Technique for controlling mechanical stress in a channel region by spacer removal 有权
    通过间隔物去除来控制通道区域的机械应力的技术

    公开(公告)号：US07314793B2

    公开(公告)日：2008-01-01

    申请号：US11047129

    申请日：2005-01-31

    申请人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

    发明人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/6653 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/7843 ,  Y10S438/938

    摘要： During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

    摘要翻译： 在形成晶体管元件期间，在离子注入和硅化之后去除侧壁间隔物或至少部分地回蚀，从而使接触蚀刻停止层与潜在的漏极和源极区域的机械耦合更有效。 因此，机械应力可以基本上由接触蚀刻步骤层引起，而不是间隔元件和蚀刻停止层的组合，从而显着地促进了沟道区域中的应力工程。 通过额外进行等离子体处理，可以在不同的晶体管器件中产生不同量的应力，而不会不利地导致工艺复杂性。

    Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics
    6.
    发明申请
    Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics 有权
    在低k层间电介质形成通孔和沟槽期间增强工艺灵活性的技术

    公开(公告)号：US20060172525A1

    公开(公告)日：2006-08-03

    申请号：US11199526

    申请日：2005-08-08

    申请人： Thomas Werner ,  Matthias Schaller ,  Massud Aminpur

    发明人： Thomas Werner ,  Matthias Schaller ,  Massud Aminpur

    IPC分类号： H01L21/467

    CPC分类号： H01L21/31138 ,  H01L21/31116 ,  H01L21/76808 ,  H01L21/76834

    摘要： In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k dielectric in that the reduction in thickness is substantially achieved during the resist removal. For this purpose, the resist plasma etch may correspondingly be controlled to obtain the desired target thickness of the etch stop layer, wherein fluorine may be provided from an external source and/or fluorine may be generated in a controlled manner from polymer layers deposited within the etch chamber.

    摘要翻译： 在用于在低k电介质层中形成通孔开口和沟槽开口的蚀刻工艺中，下层蚀刻停止层的材料去除与通过低k电介质的蚀刻分离，因为厚度的减小在 抵抗力消除。 为此，可以相应地控制抗蚀剂等离子体蚀刻以获得蚀刻停止层的期望目标厚度，其中可以从外部源提供氟，和/或​​氟可以以受控的方式从沉积在 蚀刻室。

    Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches
    8.
    发明授权
    Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches 有权
    用于通过沟槽边缘四舍五入来增强电化学沉积过程中的填充能力的技术

    公开(公告)号：US08101524B2

    公开(公告)日：2012-01-24

    申请号：US11122591

    申请日：2005-05-05

    申请人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur

    发明人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur

    IPC分类号： H01L21/462

    CPC分类号： H01L21/76804 ,  H01L21/7688

    摘要： During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.

    摘要翻译： 在低k电介质材料中形成金属线时，形成在封盖层中的沟槽的上部和低k电介质材料被处理以提供扩大的锥形或拐角四舍五入，从而显着提高填充能力 随后的金属沉积工艺。 在一个特定实施例中，在蚀刻通过覆盖层和低k电介质层之后并且在抗蚀剂移除之后执行附加蚀刻工艺。