公开(公告)号：US06429503B2

公开(公告)日：2002-08-06

申请号：US09888034

申请日：2001-06-22

申请人： Matthias Uwe Lehr ,  Rene Tews ,  Jochen Müller ,  Jürgen Lindolf

发明人： Matthias Uwe Lehr ,  Rene Tews ,  Jochen Müller ,  Jürgen Lindolf

IPC分类号： H01L2900

CPC分类号： H01L23/53257 ,  H01L23/5252 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： A connection element in an integrated circuit having a layer structure disposed between two conductive structures. The layer structure is formed by an insulating layer, which can be destroyed by application of a predetermined voltage, and a silicon layer. The insulating layer adjoins a first conductive structure made of tungsten.

摘要翻译： 集成电路中的连接元件，其具有设置在两个导电结构之间的层结构。 层结构由可以通过施加预定电压而被破坏的绝缘层和硅层形成。 绝缘层邻接由钨制成的第一导电结构。

公开(公告)号：US06458631B1

公开(公告)日：2002-10-01

申请号：US10079045

申请日：2002-02-19

申请人： Axel Brintzinger ,  Ulrich Frey ,  Jürgen Lindolf ,  Dominique Savignac ,  Stefan Dankowski ,  Matthias Lehr ,  Jochen Müller ,  Kamel Ayadi

发明人： Axel Brintzinger ,  Ulrich Frey ,  Jürgen Lindolf ,  Dominique Savignac ,  Stefan Dankowski ,  Matthias Lehr ,  Jochen Müller ,  Kamel Ayadi

IPC分类号： H01L2182

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connection of the contact (11a′).

摘要翻译： 本发明提供一种制造集成电路的方法，包括以下步骤：制备电路基板（1）; 在所述电路基板（1）中提供包括第一金属的金属化区域（10a）; 在所述金属化区域（10a）之上提供第一绝缘层（25）; 在所述绝缘层（25）中形成开口（13），以便露出所述金属化区域（10a）的所述表面的至少一部分; 在所得结构上沉积功能层（15'）; 以所述开口（13）填充的方式在所得结构上方沉积第二绝缘层（35）; 第二绝缘层（35）和功能层（15'）的抛光以便露出第一绝缘层（25）的表面; 在所述开口（13）内部的所述第二绝缘层（35）中形成接触（11a'），以与所述功能层（15'）接触。 以及提供用于电连接触头（11a'）的互连（40a）。

公开(公告)号：US06552549B1

公开(公告)日：2003-04-22

申请号：US09867253

申请日：2001-05-29

申请人： Robert Kaiser ,  Jürgen Lindolf ,  Helmut Schneider

发明人： Robert Kaiser ,  Jürgen Lindolf ,  Helmut Schneider

IPC分类号： G01R3102

CPC分类号： G11C17/18

摘要： Electrical fuses/antifuses in a semiconductor memory configuration, such as in particular a DRAM, are read, instead of with the previously conventional internal voltage, with the voltage that defines the high potential of the bit lines of a memory cell array in the semiconductor memory. The high potential of the bit lines is defined by a voltage that is reduced relative to the internal voltage of the semiconductor memory.

摘要翻译： 读取半导体存储器配置（特别是DRAM）中的电熔丝/反熔丝，而不是用先前传统的内部电压，其中定义半导体存储器中存储单元阵列的位线的高电位的电压 。 位线的高电位由相对于半导体存储器的内部电压降低的电压限定。

公开(公告)号：US06456553B1

公开(公告)日：2002-09-24

申请号：US09898233

申请日：2001-07-03

申请人： Eckhard Brass ,  Thoai-Thai Le ,  Jürgen Lindolf ,  Joachim Schnabel

发明人： Eckhard Brass ,  Thoai-Thai Le ,  Jürgen Lindolf ,  Joachim Schnabel

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C7/22 ,  G11C11/4074

摘要： A circuit configuration for switching over a receiver circuit, in particular in DRAM memories, between a standby mode and an operating mode, includes a differential amplifier functioning as a receiver receiving a control voltage derived from a reference current and generated or fed in for setting a correct operating point of said differential amplifier. A line feeds a current for generating the control voltage. Switching elements are disposed in said line for each receiver. The switching elements are permanently closed in the operating mode by an enable signal present at said switching elements for continuously supplying the current for generating the control voltage. The switching elements are closed at discrete times or periodically in the standby mode by feeding a refresh signal for discontinuously refreshing the control voltage. A DRAM memory having the circuit configuration is also provided.

摘要翻译： 用于在待机模式和操作模式之间切换接收器电路，特别是在DRAM存储器中的电路配置包括：差分放大器，用作接收从参考电流导出并产生或进给的控制电压的接收器，用于设置 所述差分放大器的正确工作点。 线路馈送用于产生控制电压的电流。 开关元件设置在每个接收器的所述线中。 开关元件在操作模式下通过存在于所述开关元件处的使能信号永久闭合，以连续地供应用于产生控制电压的电流。 开关元件在离散时间或在待机模式下周期性地闭合，通过馈送用于不连续地刷新控制电压的刷新信号。 还提供了具有电路结构的DRAM存储器。

公开(公告)号：US06756655B2

公开(公告)日：2004-06-29

申请号：US10013298

申请日：2001-12-10

申请人： Thoai-Thai Le ,  Jürgen Lindolf

发明人： Thoai-Thai Le ,  Jürgen Lindolf

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator layer has a cavity formed therein extending to the main surface of the semiconductor body. A fuse having a fusible part extends from the main surface of the semiconductor body toward an upper surface of the insulator layer at right angles to the main surface of the semiconductor body, and the fuse is embedded in the cavity. A method for producing the semiconductor configuration having the fuse is also described.

摘要翻译： 描述了一种半导体结构，其包括具有设置在半导体主体的主表面上的主表面和绝缘体层的半导体本体。 绝缘体层具有形成在其中的空腔，其延伸到半导体本体的主表面。 具有可熔部分的保险丝从半导体本体的主表面朝着与半导体主体的主表面成直角的绝缘体层的上表面延伸，并且保险丝嵌入在腔中。 还描述了具有熔丝的半导体结构的制造方法。

公开(公告)号：US06449206B2

公开(公告)日：2002-09-10

申请号：US09867292

申请日：2001-05-29

申请人： Robert Kaiser ,  Jürgen Lindolf ,  Thilo Schaffroth ,  Florian Schamberger ,  Helmut Schneider

发明人： Robert Kaiser ,  Jürgen Lindolf ,  Thilo Schaffroth ,  Florian Schamberger ,  Helmut Schneider

IPC分类号： G11C800

CPC分类号： G11C17/18

摘要： In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

摘要翻译： 为了编程可编程元件，提出以半导体电路配置将可编程元件的第一和第二连接端子连接到设置在半导体电路配置中的第一和/或第二电位器件。 以这种方式，第一和第二电位本质上可用于形成用于编程可编程元件的燃烧电压。

公开(公告)号：US06417722B1

公开(公告)日：2002-07-09

申请号：US09525820

申请日：2000-03-15

申请人： Helmut Schneider ,  Jürgen Lindolf ,  Thomas Borst ,  Hermann Ruckerbauer

发明人： Helmut Schneider ,  Jürgen Lindolf ,  Thomas Borst ,  Hermann Ruckerbauer

IPC分类号： H01L29772

CPC分类号： H01L27/088 ,  H01L21/761 ,  H01L29/1087

摘要： A sense amplifier configuration includes a semiconductor substrate, a well having a variable well potential and insulated in the semiconductor substrate, and at least one field-effect transistor in the well. The transistor has a short channel length and an adjustable threshold voltage. Locating the field-effect transistor in an insulated well with a controllable potential allows for compensation of deviations in the threshold voltage with the substrate control effect. The threshold voltage can increase with increasingly larger negative voltage values of the well potential. The threshold voltage has an actual value and a target value, and the well potential can be controlled as a function of a difference between the actual and target threshold voltage values. The well potential can vary from approximately +200 mV to −400 mV, and in steps of approximately 50 mV. The field-effect transistor has a switched-off state, and the well potential can be different from an active potential in the switched-off state of the field-effect transistor, preferably, the well potential is 0 V in the switched-off state. The field-effect transistor can be a plurality of field-effect transistors all disposed in the well. The semiconductor substrate, the well, and the field-effect transistor can be fabricated by ion implantation.

摘要翻译： 读出放大器配置包括半导体衬底，具有可变阱电位且在半导体衬底中绝缘的阱以及阱中的至少一个场效应晶体管。 晶体管具有短通道长度和可调阈值电压。 将场效应晶体管定位在具有可控电位的绝缘阱中，可以利用衬底控制效应来补偿阈值电压的偏差。 阈值电压可以随着井电势的负电压值越来越大而增加。 阈值电压具有实际值和目标值，并且阱电位可以作为实际阈值电压值和目标阈值电压值之间的差值的函数进行控制。 阱电位可以从大约+ 200mV到-400mV，步长约50mV。 场效应晶体管具有关断状态，并且阱电位可以与场效应晶体管的关断状态下的有效电位不同，优选在关断状态下阱电位为0V 。 场效应晶体管可以是全部设置在阱中的多个场效应晶体管。 半导体衬底，阱和场效应晶体管可以通过离子注入来制造。

公开(公告)号：US06788129B2

公开(公告)日：2004-09-07

申请号：US10301090

申请日：2002-11-20

申请人： Jörg Peter ,  Jürgen Lindolf ,  Florian Schamberger ,  Helmut Schneider

发明人： Jörg Peter ,  Jürgen Lindolf ,  Florian Schamberger ,  Helmut Schneider

IPC分类号： H01H3776

CPC分类号： G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

摘要翻译： 集成电路具有可通过编程改变的电互连电阻的可编程元件。 用于评估电互连电阻的评估电路连接到可编程元件。 可编程元件的电互连电阻由评估电路读出和评估。 利用与评估电路连接的微调电路，根据由评估电路读出的电互连电阻来调节评估电路的工作点。 以这种方式，可以独立于技术波动来读出和评估可编程元件的状态。

公开(公告)号：US06768139B2

公开(公告)日：2004-07-27

申请号：US10217184

申请日：2002-08-12

申请人： Helmut Fischer ,  Jürgen Lindolf

发明人： Helmut Fischer ,  Jürgen Lindolf

IPC分类号： H01L31072

CPC分类号： G05F3/30 ,  H01L29/7327

摘要： A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

摘要翻译： 用于带隙电路的晶体管配置被配置为npn晶体管的形式。 被埋置的n型阱包围的绝缘p型阱用作基极端子。 n型阱构成发射极端子。 在p型阱中形成用作集电极端子的负掺杂区域。 所使用的结构存在于DRAM工艺中，因此可用于在带隙电路中形成npn晶体管作为覆盖二极管。

公开(公告)号：US06717200B1

公开(公告)日：2004-04-06

申请号：US09408688

申请日：1999-09-30

申请人： Florian Schamberger ,  Helmut Schneider ,  Jürgen Lindolf ,  Thoai-Thai Le

发明人： Florian Schamberger ,  Helmut Schneider ,  Jürgen Lindolf ,  Thoai-Thai Le

IPC分类号： H01L31119

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/42368 ,  H01L29/7827

摘要： A vertical MOS field effect transistor includes a gate disposed in a trench, a channel, and a source and a drain disposed in the substrate on the trench wall. The gate annularly surrounds a drain terminal which extends from the substrate surface as far as the drain disposed on the trench bottom. It is possible to produce vertical transistors with different channel lengths on a substrate with trenches of different widths by employing oblique implantation when producing the gate. A method of producing the vertical field effect transistor is also provided.

摘要翻译： 垂直MOS场效应晶体管包括设置在沟槽中的栅极，沟道以及设置在沟槽壁上的衬底中的源极和漏极。 栅极环形地围绕从衬底表面延伸到漏极设置在沟槽底部的漏极端子。 通过在制造栅极时采用倾斜注入，可以在具有不同宽度的沟槽的衬底上制造具有不同沟道长度的垂直晶体管。 还提供了一种制造垂直场效应晶体管的方法。