公开(公告)号：US09978692B2

公开(公告)日：2018-05-22

申请号：US14997048

申请日：2016-01-15

Applicant: MediaTek Inc.

Inventor： PoHao Chang ,  Chun-Wei Chang ,  Ching-Chih Li

IPC: H05K1/02 ,  H01L23/552 ,  H01L23/66 ,  H01L23/528 ,  H01L27/12 ,  H04B3/32 ,  H01L23/498 ,  H05K3/46 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L27/12 ,  H01L2223/6688 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/3025 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243 ,  H05K3/46

Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins, and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The pins are coupled to a device via a plurality of conductive traces of a printed circuit board (PCB). The control signals control each of the driving units to selectively provide the data or one specific shielding pattern via the corresponding pin and the corresponding conductive trace of PCB to the device.

公开(公告)号：US11573264B2

公开(公告)日：2023-02-07

申请号：US16828925

申请日：2020-03-24

Applicant: MEDIATEK INC.

Inventor： Ching-Chih Li ,  Sheng-Ming Chang

IPC: G01R31/28

Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

公开(公告)号：US20150379184A1

公开(公告)日：2015-12-31

申请号：US14843094

申请日：2015-09-02

Applicant: MediaTek Inc

Inventor： Fu-Kang PAN ,  Nan-Cheng CHEN ,  Shih-Chieh LIN ,  HUI-CHI TANG ,  Ying LIU ,  Yang LIU ,  Ching-Chih Li

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

Abstract: A printed circuit board (PCB) is provided. The PCB has a specific routing module, having a first chip, a memory chip, and a plurality of traces designed for interconnection between the first chip and the memory chip according to a routing configuration between the first chip and the memory chip. The memory chip is a dynamic random access memory (DRAM) with a memory type, the specific routing module is obtained from a module group comprising a plurality of routing modules according to a plurality of PCB parameters, and module group is obtained from a database according to the memory type of the DRAM.

Abstract translation: 提供印刷电路板（PCB）。 PCB具有特定的路由模块，具有根据第一芯片和存储芯片之间的布线配置的第一芯片，存储器芯片和设计用于第一芯片和存储器芯片之间的互连的多条迹线。 存储器芯片是具有存储器类型的动态随机存取存储器（DRAM），根据多个PCB参数从包括多个路由模块的模块组获得特定路由模块，并且从数据库获得模块组 到DRAM的存储器类型。

公开(公告)号：US20150379180A1

公开(公告)日：2015-12-31

申请号：US14843113

申请日：2015-09-02

Applicant: MediaTek Inc

Inventor： Fu-Kang PAN ,  Nan-Cheng CHEN ,  Shih-Chieh LIN ,  HUI-CHI TANG ,  Ying LIU ,  Yang LIU ,  Ching-Chih Li

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

Abstract: A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

Abstract translation: 提供了印刷电路板（PCB）的布局方法。 该方法获得要安装在PCB上的动态随机存取存储器（DRAM）的存储器类型，根据DRAM的存储器类型从数据库获取模块组，其中模块组包括多个路由模块，获得 多个PCB参数，根据PCB参数从模块组中选择特定的路由模块，并将特定路由模块实现为PCB制造的布局设计。 特定路由模块包括关于主芯片，存储芯片和主芯片与存储芯片之间的布线配置的布局信息。

公开(公告)号：US20200326368A1

公开(公告)日：2020-10-15

申请号：US16828925

申请日：2020-03-24

Applicant: MEDIATEK INC.

Inventor： Ching-Chih Li ,  Sheng-Ming Chang

IPC: G01R31/28

Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

公开(公告)号：US20230125573A1

公开(公告)日：2023-04-27

申请号：US18087832

申请日：2022-12-23

Applicant: MEDIATEK INC.

Inventor： Ching-Chih Li ,  Sheng-Ming Chang

IPC: G01R31/28

Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

公开(公告)号：US10581414B2

公开(公告)日：2020-03-03

申请号：US15274473

申请日：2016-09-23

Applicant: MediaTek Inc.

Inventor： Chun-Neng Liao ,  Meng-Hsin Chiang ,  Chun-Wei Chang ,  Chee-Kong Ung ,  Ching-Chih Li

IPC: H03K5/1252 ,  H03H7/06 ,  H01L25/16 ,  H01L23/64 ,  H03H3/02

Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.

公开(公告)号：US09846756B2

公开(公告)日：2017-12-19

申请号：US14843113

申请日：2015-09-02

Applicant: MediaTek Inc

Inventor： Fu-Kang Pan ,  Nan-Cheng Chen ,  Shih-Chieh Lin ,  Hui-Chi Tang ,  Ying Liu ,  Yang Liu ,  Ching-Chih Li

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

Abstract: A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

公开(公告)号：US20160218092A1

公开(公告)日：2016-07-28

申请号：US14920883

申请日：2015-10-23

Applicant: Mediatek Inc.

Inventor： Po-Hao Chang ,  Chun-Wei Chang ,  Ching-Chih Li

IPC: H01L25/16 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/19104 ,  H01L2924/19105

Abstract: A chip package includes a first die encapsulated by a molding compound; a board comprising a chip mounting surface; a redistributed layer (RDL) structure on an active surface of the first die and between the die and the chip mounting surface; and a discrete passive device embedded in the molding compound and situated in close proximity to a side edge of the first die.

Abstract translation: 芯片封装包括由模塑料封装的第一模具; 包括芯片安装表面的板; 在所述第一管芯的有效表面上以及所述管芯和所述芯片安装表面之间的再分布层（RDL）结构; 以及嵌入在模制化合物中且位于第一模具的侧边缘附近的分立无源器件。