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Patent Agency Ranking
公开(公告)号：US09754636B2
公开(公告)日：2017-09-05
申请号：US14871859
申请日：2015-09-30
Applicant: MediaTek Inc.
Inventor： Tai-Ying Jiang , Jien-Jia Su , Szu-Ying Cheng , Chun-Fang Peng , Fumin Huang
CPC classification number: G11C5/147 , G06F1/26 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402
Abstract: One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion.
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2.发明申请MULTI-CHANNEL MEMORY SYSTEM USING ASYMMETRIC CHANNEL FREQUENCY SCALING AND RELATED POWER MANAGEMENT METHOD 有权使用不对称通道频率分级和相关电源管理方法的多通道存储器系统公开(公告)号：US20160125923A1
公开(公告)日：2016-05-05
申请号：US14530837
申请日：2014-11-03
Applicant: MEDIATEK INC.
Inventor： Ming-Hsien Lee , Yun-Ching Li , Yi-Chih Huang , Chun-Fang Peng
CPC classification number: G11C8/18 , G06F12/0607 , G06F13/1684 , G06F13/1689 , G11C5/14 , G11C7/1072 , G11C8/06 , G11C8/08 , Y02D10/13 , Y02D10/14
Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.
Abstract translation: 多通道存储器系统具有存储器件，多个通道和控制电路。 存储装置具有多个存储器存储空间。 通道分别耦合到存储器存储空间，其中每个通道被配置为用作独立地访问对应的存储器存储空间的存储器接口。 控制电路分别控制通道上时钟的时钟频率。 在同一时间点，信道至少包括以由控制电路设置的第一时钟频率操作的第一信道和在同一时间点由控制电路设置的第二时钟频率操作的第二信道，以及第二时钟 频率与第一个时钟频率不同。
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公开(公告)号：US20160027480A1
公开(公告)日：2016-01-28
申请号：US14871859
申请日：2015-09-30
Applicant: MediaTek Inc.
Inventor： Tai-Ying Jiang , Jien-Jia Su , Szu-Ying Cheng , Chun-Fang Peng , Fumin Huang
CPC classification number: G11C5/147 , G06F1/26 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402
Abstract: One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion.
Abstract translation: 当第一电路的操作至少部分地基于与第二配置设置相关联的一个或多个值时，与第一电路的第一配置设置相关联的一个或多个值可被存储在第一组一个或多个寄存器中 存储在第二组一个或多个寄存器中。 响应于接收到第一电路的工作频率或电压变化的指示，可以通过加载与第一配置相关联的一个或多个值来改变存储在一个或多个寄存器的第二组中的一个或多个值 将存储在第一组一个或多个寄存器中的设置以并行方式存储到第二组一个或多个寄存器中。
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公开(公告)号：US09747963B2
公开(公告)日：2017-08-29
申请号：US14530837
申请日：2014-11-03
Applicant: MEDIATEK INC.
Inventor： Ming-Hsien Lee , Yun-Ching Li , Yi-Chih Huang , Chun-Fang Peng
CPC classification number: G11C8/18 , G06F12/0607 , G06F13/1684 , G06F13/1689 , G11C5/14 , G11C7/1072 , G11C8/06 , G11C8/08 , Y02D10/13 , Y02D10/14
Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.
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5.发明申请INTEGRATED CIRCUIT HAVING AT LEAST ONE FUNCTIONAL CIRCUIT BLOCK OPERATING IN MULTI-SOURCE POWER DOMAIN AND RELATED SYSTEM WITH POWER MANAGEMENT 审中-公开具有电源管理的多源功率域和相关系统中的至少一个功能电路块操作的集成电路公开(公告)号：US20150028940A1
公开(公告)日：2015-01-29
申请号：US14325284
申请日：2014-07-07
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Kin Lam Tong , Chun-Fang Peng
CPC classification number: H01L23/5286 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit has a semiconductor layer, at least one metal layer, a plurality of functional circuit blocks formed on the semiconductor layer, and a power mesh formed on the at least one metal layer. The power mesh has a specific area corresponding to a specific functional circuit block of the functional circuit blocks. The specific area at least has a first power trunk of a first power source and a second power trunk of a second power source distributed therein.
Abstract translation: 集成电路具有半导体层，至少一个金属层，形成在半导体层上的多个功能电路块，以及形成在该至少一个金属层上的功率栅。 功率网具有对应于功能电路块的特定功能电路块的特定区域。 特定区域至少具有分配在其中的第一电源的第一电力中继线和第二电源的第二电力中继线。
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