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公开(公告)号：US12003245B2
公开(公告)日：2024-06-04
申请号：US17902917
申请日：2022-09-05
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Yi-Hsien Cho
IPC: H03L7/08 , H03L7/085 , H04B1/7073 , H04L7/00 , H04L7/033 , H04L27/227
CPC classification number: H03L7/0807 , H03L7/085 , H04B1/7073 , H04L7/0025 , H04L7/0331 , H04L27/2271 , H04B2201/7073
Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.
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公开(公告)号：US20130154701A1
公开(公告)日：2013-06-20
申请号：US13769810
申请日：2013-02-18
Applicant: Mediatek Inc.
Inventor： Yu-Li Hsueh , Yi-Hsien Cho , Jing-Hong Conan Zhan
IPC: H03L5/00
CPC classification number: H03L5/00 , H03L7/089 , H03L7/0895 , H03L7/0896 , H03L7/093
Abstract: A phase/frequency detector for control signal to controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.
Abstract translation: 用于控制电荷泵的控制信号的相位/频率检测器包括：核心电路，被布置成根据参考时钟信号和输入时钟信号之间的相位/频率差输出第一相位信号和第二相位信号; 以及定时电路，其耦合到所述核心电路并被布置成根据所述第一相位信号和所述第二相位信号产生用于控制所述电荷泵的第一控制信号和第二控制信号，其中，所述第一控制信号和所述第二控制信号中的仅一个 当参考时钟信号和输入时钟信号在相位上基本上相同时，控制信号指示使能操作。
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公开(公告)号：US20240283458A1
公开(公告)日：2024-08-22
申请号：US18648493
申请日：2024-04-29
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Yi-Hsien Cho
IPC: H03L7/08 , H03L7/085 , H04B1/7073 , H04L7/00 , H04L7/033 , H04L27/227
CPC classification number: H03L7/0807 , H03L7/085 , H04B1/7073 , H04L7/0025 , H04L7/0331 , H04L27/2271 , H04B2201/7073
Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.
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Patent Agency Ranking
公开(公告)号：US20170141779A1
公开(公告)日：2017-05-18
申请号：US15262014
申请日：2016-09-12
Applicant: MEDIATEK INC.
Inventor： Tse-Hsien Yeh , Yi-Hsien Cho
CPC classification number: H03L7/0807 , H03L7/0814 , H03L7/093 , H04L7/033
Abstract: A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.
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公开(公告)号：US08766684B2
公开(公告)日：2014-07-01
申请号：US13769810
申请日：2013-02-18
Applicant: Mediatek Inc.
Inventor： Yu-Li Hsueh , Yi-Hsien Cho , Jing-Hong Conan Zhan
IPC: H03L7/06
CPC classification number: H03L5/00 , H03L7/089 , H03L7/0895 , H03L7/0896 , H03L7/093
Abstract: A phase/frequency detector for controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.
Abstract translation: 用于控制电荷泵的相位/频率检测器包括：核心电路，被布置成根据参考时钟信号和输入时钟信号之间的相位/频率差输出第一相位信号和第二相位信号; 以及定时电路，其耦合到所述核心电路并被布置成根据所述第一相位信号和所述第二相位信号产生用于控制所述电荷泵的第一控制信号和第二控制信号，其中，所述第一控制信号和所述第二控制信号中的仅一个 当参考时钟信号和输入时钟信号在相位上基本上相同时，控制信号指示使能操作。
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公开(公告)号：US20230163765A1
公开(公告)日：2023-05-25
申请号：US17902917
申请日：2022-09-05
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Yi-Hsien Cho
IPC: H03L7/08 , H03L7/085 , H04L7/033 , H04L7/00 , H04B1/7073
CPC classification number: H03L7/0807 , H03L7/085 , H04L7/0331 , H04L7/0025 , H04B1/7073 , H04B2201/7073
Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.
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公开(公告)号：US09923564B2
公开(公告)日：2018-03-20
申请号：US15262014
申请日：2016-09-12
Applicant: MEDIATEK INC.
Inventor： Tse-Hsien Yeh , Yi-Hsien Cho
CPC classification number: H03L7/0807 , H03L7/0814 , H03L7/093 , H04L7/033
Abstract: A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.
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8.发明授权Interpolator and interpolation cells with non-uniform driving capabilities therein 有权具有不均匀驱动能力的插值单元和内插单元公开(公告)号：US09306551B2
公开(公告)日：2016-04-05
申请号：US13747012
申请日：2013-01-22
Applicant: MediaTek Inc.
Inventor： Yi-Hsien Cho , Kuan-Hua Chao
Abstract: An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.
Abstract translation: 插值器包括插值单元。 每个插值单元包括第一驱动单元和第二驱动单元。 第一驱动单元包括用于将输出端子选择性地耦合到高电压的第一上拉电路，用于选择性地将输出端子耦合到低电压的第一下拉电路和用于选择性地使能/禁用的一对第一开关 第一上拉电路和第一下拉电路。 第二驱动单元包括用于将输出端子选择性地耦合到高电压的第二上拉电路，用于选择性地将输出端子耦合到低电压的第二下拉电路和用于选择性地启用/禁用的一对第二开关 第二上拉电路和第二下拉电路。 第一和第二上拉电路的驱动能力并不全部相等，和/或第一和第二下拉电路的驱动能力并非全部相等。
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