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    HARDWARE-ACCELERATED DECODING OF SCALABLE VIDEO BITSTREAMS
    2.
    发明申请
    HARDWARE-ACCELERATED DECODING OF SCALABLE VIDEO BITSTREAMS 有权
    可扩展视频点阵的硬件加速解码

    公开(公告)号：US20130156101A1

    公开(公告)日：2013-06-20

    申请号：US13329093

    申请日：2011-12-16

    申请人： Mei-Hsuan Lu ,  Yongjun Wu ,  Ming-Chieh Lee ,  Gary J. Sullivan

    发明人： Mei-Hsuan Lu ,  Yongjun Wu ,  Ming-Chieh Lee ,  Gary J. Sullivan

    IPC分类号： H04N7/32

    CPC分类号： H04N19/42 ,  H04N19/30 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44

    摘要： In various respects, hardware-accelerated decoding is adapted for decoding of video that has been encoded using scalable video coding. For example, for a given picture to be decoded, a host decoder determines whether a corresponding base picture will be stored for use as a reference picture. If so, the host decoder directs decoding with an accelerator such that the some of the same decoding operations can be used for the given picture and the reference base picture. Or, as another example, the host decoder groups encoded data associated with a given layer representation in buffers. The host decoder provides the encoded data for the layer to the accelerator. The host decoder repeats the process layer-after-layer in the order that layers appear in the bitstream, according to a defined call pattern for an acceleration interface, which helps the accelerator determine the layers with which buffers are associated.

    摘要翻译： 在各个方面，硬件加速解码适用于已经使用可分级视频编码进行编码的视频的解码。 例如，对于要解码的给定图像，主机解码器确定相应的基本图像是否将被存储以用作参考图像。 如果是这样，则主机解码器用加速器指示解码，使得可以使用一些相同的解码操作用于给定图像和参考基本图像。 或者，作为另一示例，主机解码器对与缓冲器中的给定层表示相关联的编码数据进行分组。 主机解码器将该层的编码数据提供给加速器。 主机解码器根据用于加速接口的定义的呼叫模式按照层出现在比特流中的顺序重复进程层，这有助于加速器确定与哪些缓冲器相关联的层。

    FEATURES OF INTRA BLOCK COPY PREDICTION MODE FOR VIDEO AND IMAGE CODING AND DECODING
    3.
    发明申请
    FEATURES OF INTRA BLOCK COPY PREDICTION MODE FOR VIDEO AND IMAGE CODING AND DECODING 审中-公开
    用于视频和图像编码和解码的内部块复制预测模式的特征

    公开(公告)号：US20160241868A1

    公开(公告)日：2016-08-18

    申请号：US15025128

    申请日：2013-10-14

    申请人： Bin LI ,  Jizheng XU ,  Gary J. SULLIVAN ,  MICROSOFT TECHNOLOGY LICENSING, LLC

    发明人： Bin Li ,  Jizheng Xu ,  Gary J. Sullivan

    IPC分类号： H04N19/52 ,  H04N19/91 ,  H04N19/57 ,  H04N19/82 ,  H04N19/86 ,  H04N19/56

    CPC分类号： H04N19/52 ,  H04N19/56 ,  H04N19/57 ,  H04N19/593 ,  H04N19/70 ,  H04N19/82 ,  H04N19/86 ,  H04N19/91

    摘要： Innovations in intra block copy (“BC”) prediction mode facilitate intra BC prediction that is more effective in terms of rate-distortion performance and/or computational efficiency of encoding and decoding. For example, some of the innovations provide ways to select block vector (“BV”) values more effectively. Other innovations provide ways to encode/decode BV values more efficiently. Still other innovations address how to perform in-loop deblock filtering when a block has intra BC prediction mode, or address how to perform intra BC prediction when constrained intra prediction is enabled.

    摘要翻译： 块内复制（“BC”）预测模式的创新促进了在速率失真性能和/或编码和解码的计算效率方面更有效的BC内预测。 例如，一些创新提供了更有效地选择块向量（“BV”）值的方法。 其他创新提供了更有效地对BV值进行编码/解码的方法。 还有其他创新涉及当块具有BC内预测模式时如何执行循环去块滤波，或者当限制帧内预测启用时，如何执行帧内BC预测。

    Reducing latency in video encoding and decoding
    4.
    发明授权
    Reducing latency in video encoding and decoding 有权
    减少视频编码和解码中的延迟

    公开(公告)号：US08837600B2

    公开(公告)日：2014-09-16

    申请号：US13270969

    申请日：2011-10-11

    申请人： Gary J. Sullivan

    发明人： Gary J. Sullivan

    IPC分类号： H04N7/12 ,  H04N19/31 ,  H04N19/46 ,  H04N19/103 ,  H04N19/172 ,  H04N19/70

    CPC分类号： H04N19/70 ,  H04N19/103 ,  H04N19/15 ,  H04N19/172 ,  H04N19/184 ,  H04N19/31 ,  H04N19/44 ,  H04N19/46 ,  H04N19/88

    摘要： Techniques and tools for reducing latency in video encoding and decoding by constraining latency due to reordering of video frames, and by indicating the constraint on frame reordering latency with one or more syntax elements that accompany encoded data for the video frames. For example, a real-time communication tool with a video encoder sets a syntax element that indicates a constraint on frame reordering latency, which is consistent with inter-frame dependencies between multiple frames of a video sequence, then outputs the syntax element. A corresponding real-time communication tool with a video decoder receives the syntax element that indicates the constraint on frame reordering latency, determines the constraint on frame reordering latency based on the syntax element, and uses the constraint on frame reordering latency to determine when a reconstructed frame is ready for output (in terms of output order).

    摘要翻译： 技术和工具，用于通过限制由于视频帧的重新排序而引起的等待时间，以及通过与伴随视频帧的编码数据的一个或多个语法元素指示对帧重排序延迟的约束来减少视频编码和解码中的延迟。 例如，具有视频编码器的实时通信工具设置指示对帧重新排序等待时间的约束的语法元素，其与视频序列的多个帧之间的帧间依赖性一致，然后输出语法元素。 具有视频解码器的对应的实时通信工具接收指示对帧重新排序等待时间的约束的语法元素，基于语法元素确定对帧重新排序等待时间的约束，并且使用对帧重排序等待时间的约束来确定何时重构 帧准备输出（按照输出顺序）。

    Reduced DC gain mismatch and DC leakage in overlap transform processing
    6.
    发明授权
    Reduced DC gain mismatch and DC leakage in overlap transform processing 有权
    在重叠变换处理中降低了直流增益失配和直流泄漏

    公开(公告)号：US08275209B2

    公开(公告)日：2012-09-25

    申请号：US12571365

    申请日：2009-09-30

    申请人： Daniel Schonberg ,  Shankar L. Regunathan ,  Shijun Sun ,  Gary J. Sullivan ,  Zhi Zhou ,  Sridhar Srinivasan

    发明人： Daniel Schonberg ,  Shankar L. Regunathan ,  Shijun Sun ,  Gary J. Sullivan ,  Zhi Zhou ,  Sridhar Srinivasan

    IPC分类号： G06K9/36

    CPC分类号： G06F17/147 ,  H04N19/117 ,  H04N19/122 ,  H04N19/14 ,  H04N19/176 ,  H04N19/60 ,  H04N19/86

    摘要： In certain embodiments, overlap operators are applied during encoding and/or decoding of digital media, where the overlap operators have reduced DC gain mismatch and/or DC leakage between interior overlap operators and overlap operators at the edge and/or corner. In other embodiments, information indicating a selected tile boundary option for overlap processing can be encoded and/or decoded. The selected tile boundary option indicates one of a hard tile boundary option and a soft tile boundary option for processing with overlap operators. Overlap transform processing can then be applied based at least in part on the selected tile boundary option.

    摘要翻译： 在某些实施例中，在数字媒体的编码和/或解码期间应用重叠运算符，其中重叠运算符在边缘和/或角落处内部重叠运算符和重叠运算符之间具有降低的DC增益失配和/或DC泄漏。 在其他实施例中，可以编码和/或解码指示用于重叠处理的所选择的瓦片边界选项的信息。 所选的瓦片边界选项指示用于使用重叠运算符进行处理的硬瓦片边界选项和软瓦片边界选项之一。 然后可以至少部分地基于所选择的瓦片边界选项来应用重叠变换处理。

    Signaling and use of chroma sample positioning information
    7.
    发明授权
    Signaling and use of chroma sample positioning information 有权
    信号和使用色度样本定位信息

    公开(公告)号：US08054886B2

    公开(公告)日：2011-11-08

    申请号：US11772070

    申请日：2007-06-29

    申请人： Sridhar Srinivasan ,  Chengjie Tu ,  Shankar Regunathan ,  Gary J. Sullivan

    发明人： Sridhar Srinivasan ,  Chengjie Tu ,  Shankar Regunathan ,  Gary J. Sullivan

    IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/20 ,  H04N7/01

    CPC分类号： H04N19/186 ,  H04N19/46 ,  H04N19/63 ,  H04N19/70

    摘要： Rules for the signaling and interpretation of chroma position are described. One rule, called the short rule, defines fifteen discrete chroma centering positions and corresponding four-bit syntax element. Another rule, called the extended rule, defines 81 discrete chroma centering positions and corresponding seven-bit syntax elements. A described method includes receiving digital media data at a digital media encoder, determining chroma position information for the received digital media data, and representing the chroma position information with one or more syntax elements in an encoded bitstream. The one or more syntax elements are operable to communicate the chroma position information to a digital media decoder. The chroma position information facilitates an image rotation or flip.

    摘要翻译： 描述色度位置信号和解释规则。 称为短规则的一个规则定义了十五个离散色度对中位置和相应的四位语法元素。 称为扩展规则的另一个规则定义了81个离散色度对中位置和相应的七位语法元素。 所描述的方法包括在数字媒体编码器处接收数字媒体数据，确定接收到的数字媒体数据的色度位置信息，并用编码比特流中的一个或多个语法元素表示色度位置信息。 一个或多个语法元素可操作以将色度位置信息传送到数字媒体解码器。 色度位置信息有助于图像旋转或翻转。

    Compressed timing indicators for media samples
    8.
    发明授权
    Compressed timing indicators for media samples 有权

    公开(公告)号：US07633551B2

    公开(公告)日：2009-12-15

    申请号：US11379025

    申请日：2006-04-17

    申请人： Gary J. Sullivan

    发明人： Gary J. Sullivan

    IPC分类号： H04N5/06 ,  H04N9/475 ,  H04N5/91

    CPC分类号： H04N21/4305 ,  H04B1/66 ,  H04N7/52 ,  H04N21/23608 ,  H04N21/242 ,  H04N21/4344 ,  H04N21/8547

    摘要： A first frame of data is encoded and a first timestamp associated with the first frame of data is generated. The first timestamp includes complete timing information. The first frame of data and the associated first timestamp is transmitted to a destination. A second frame of data is encoded and a second timestamp associated with the second frame of data is generated. The second timestamp includes a portion of the complete timing information. The second frame of data and the associated second timestamp is then transmitted to the destination. Additional frames of data are encoded and additional timestamps associated with the additional frames of data are generated. The majority of the additional timestamps include a portion of the complete timing information.