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1.发明授权Predictable updating of a baud divisor of an asynchronous serial port during data reception 有权在数据接收期间可异步串行端口的波特除数的可预测的更新公开(公告)号：US06850561B1
公开(公告)日：2005-02-01
申请号：US09590353
申请日：2000-06-08
CPC分类号： H04L25/45
摘要： A microcontroller employs an asynchronous serial port for predictably updating a baud divisor during data reception. A write enable to the baud counter ensures that the current value of the baud count in the baud counter is greater than a predetermined number of clocks so that the working baud divisor to be loaded from the working baud divisor register is stabilized. The working baud divisor register is updated during data reception by the serial port by a software write to a visible baud divisor register provided the working baud divisor in the working baud divisor register is not being used to load the baud counter. A working baud divisor register thereby maintains a value guaranteed to be stable by the time a baud counter needs to be reloaded. A visible baud divisor register and the baud counter can be on different, possibly asynchronous clocks.
摘要翻译： 微控制器采用异步串行端口在数据接收期间可预测地更新波特除数。 对波特率计数器的写使能可确保波特率计数器当前的波特率值大于预定数量的时钟，从而工作波特率寄存器中加载的工作波特率被稳定。 如果工作波特率寄存器中的工作波特除数未用于加载波特率计数器，则工作波特率寄存器在数据接收期间通过软件写入可见波特率除数寄存器进行更新。 一个工作波特除数寄存器因此在保持波特率计数器需要重新加载的时间内保持一个保证稳定的值。 可见波特除数寄存器和波特率计数器可以在不同的可能的异步时钟上。
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公开(公告)号：US06366610B1
公开(公告)日：2002-04-02
申请号：US09080336
申请日：1998-05-15
IPC分类号： H04B1700
CPC分类号： G06F13/385 , H04L25/0262
摘要： An asynchronous receiver/transmitter provides autobauding with adjustment to a programmable baud rate. A baud divisor is calculated based on a detected size of a start bit. The asynchronous receiver/transmitter provides a plurality of baud divisor replacement registers, each register storing a baud divisor threshold and a baud divisor replacement. The baud divisor is compared to the plurality of programmed baud divisor thresholds. Based on the performed hardware comparison, the baud divisor is automatically replaced by a baud divisor replacement for a particular baud divisor range defined by a baud divisor threshold and including the baud divisor. The baud rate corresponding to this baud divisor replacement represents the appropriate baud rate. Autobauding with adjustment to a programmed baud rate corrects for measurement inaccuracies with respect to the start bit size. Autobauding with adjustment to a programmed baud rate also permits an asynchronous receiver/transmitter to reliably support high speed baud rates. Further, the programmable nature of the baud divisor thresholds and baud divisor replacements permits an asynchronous receiver/transmitter to support autubauding at multiple asynchronous receiver/transmitter frequencies.
摘要翻译： 异步接收器/发送器通过对可编程波特率进行调整来提供自动波特率。 基于检测到的起始位的大小来计算波特除数。 异步接收器/发送器提供多个波特除数替换寄存器，每个寄存器存储波特除数阈值和波特除数替换。 波特除数与多个编程的波特除数阈值进行比较。 根据执行的硬件比较，波特除数由波特除数阈值和波特除数定义的特定波特率除数的波特除数自动替换。 对应于该波特率除数的波特率代表相应的波特率。 通过调整编程的波特率进行自动波特率校正相对于起始位大小的测量不准确。 通过调整编程波特率的自动波特率还允许异步接收器/发送器可靠地支持高速波特率。 此外，波特率除数阈值和波特除数替换的可编程性允许异步接收器/发送器在多个异步接收器/发射器频率上支持自动调谐。
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3.发明授权Data compression or decompressions during DMA transfer between a source and a destination by independently controlling the incrementing of a source and a destination address registers 失效通过独立控制源和目的地址寄存器的递增，在源和目的地之间的DMA传输期间进行数据压缩或解压缩公开(公告)号：US06385670B1
公开(公告)日：2002-05-07
申请号：US09088133
申请日：1998-06-01
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the “compressive” DMA.
摘要翻译： 微控制器包括直接存储器访问单元，其压缩和解压缩数据并从一个存储器块传送到另一个存储器。 具体来说，可以读取字长数据，丢弃一个字节，并作为连续的字节大小数据存储。 这可以与扩展的读取和扩展写入异步串行端口一起使用，它将状态信息和数据一起存储。 处理状态信息后，通过执行“压缩”DMA来剥离状态。
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公开(公告)号：US5862148A
公开(公告)日：1999-01-19
申请号：US798249
申请日：1997-02-11
CPC分类号： G06F11/3656
摘要： A microcontroller integrates an internal memory accessible by the cores included thereon. Logic within the microcontroller compares memory addresses generated by the cores to values in a configuration register specifying a memory address range in which the internal memory resides. The logic generates a chip select signal to the internal memory if the memory address generated resides within the specified address range to enable accesses by the cores to the internal memory. The integrated circuit may be configured in a debug mode wherein the chip select signal is inhibited to the internal memory, however the chip select signal is provided external to the integrated circuit on a pin. The chip select signal may then be used to select an external memory which serves to overlay the internal memory address range. Thus the debug mode allows instruction code and data to reside in the external memory rather than the internal memory while in the debug mode. This facilitates debugging of the code since the contents of the external memory may be examined, for example by an in-circuit emulator, in a less intrusive manner than the contents of the internal memory may be examined. The debug mode may be enabled by asserting a signal upon a predefined pin at the conclusion of reset of the microcontroller. By providing the predefined pin for placing the microcontroller into the debug mode, the microcontroller may be placed into the debug mode for debug purposes without changing the instruction code being executed thereon. Furthermore, the in-circuit emulator need not have knowledge of the internal memory address range.
摘要翻译： 微控制器集成了由其上包括的核可访问的内部存储器。 微控制器内的逻辑电路将内核产生的内存地址与配置寄存器中的值进行比较，指定内部存储器所在的内存地址范围。 如果产生的存储器地址驻留在指定的地址范围内，则逻辑将产生芯片选择信号到内部存储器，以使内核能够访问内部存储器。 集成电路可以配置在调试模式，其中芯片选择信号被禁止到内部存储器，然而芯片选择信号被提供在引脚上的集成电路的外部。 然后可以使用芯片选择信号来选择用于覆盖内部存储器地址范围的外部存储器。 因此，在调试模式下，调试模式允许指令代码和数据驻留在外部存储器而不是内部存储器中。 这有利于代码的调试，因为外部存储器的内容可以例如通过在线仿真器以比内部存储器的内容更少侵入的方式进行检查。 在微控制器复位结束时，通过在预定义的引脚上断言一个信号可以使能调试模式。 通过提供用于将微控制器置于调试模式的预定义引脚，可以将微控制器置于调试模式以进行调试，而不改变在其上执行的指令代码。 此外，在线仿真器不需要了解内部存储器地址范围。
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公开(公告)号：US06332173B2
公开(公告)日：2001-12-18
申请号：US09183945
申请日：1998-10-31
申请人： Melanie D. Typaldos
发明人： Melanie D. Typaldos
IPC分类号： G06F132
CPC分类号： G06F11/10 , G06F13/4226
摘要： An asynchronous serial port provides automatic parity generation and detection in frames supporting address bits. In data frames comprising a variable number of data bits, the parity bit is located immediately following the last data bit and before the address bit. Parity generation is performed automatically based only on the preceding data bits. Parity detection allows interrupts to be generated directly from the parity bit received. Further, parity generation and detection is not dependent on the number of bits in the data frame.
摘要翻译： 异步串行端口在支持地址位的帧中提供自动奇偶校验生成和检测。 在包括可变数量的数据位的数据帧中，奇偶校验位紧邻最后一个数据位并在地址位之前。 仅基于前面的数据位自动执行奇偶校验生成。 奇偶检测允许直接从接收的奇偶校验位产生中断。 此外，奇偶校验生成和检测不依赖于数据帧中的比特数。
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公开(公告)号：US06260162B1
公开(公告)日：2001-07-10
申请号：US09183915
申请日：1998-10-31
IPC分类号： G06F1100
CPC分类号： G06F11/0757
摘要： A processor-oriented device provides a watchdog timer having a test mode programmable reset. When the device is placed in a test mode by pulling a test mode hardware pin during a reset of the timer and then an appropriate write key is provided to the timer, a watchdog timer reset count is writeable, allowing for a programmable duration for a watchdog timer reset. The watchdog timer reset count may be a reset duration value maintained by a watchdog timer reset counter. Based on both a test mode signal from watchdog timer test mode enable logic and a write key, watchdog timer reset write enable logic enables writes to the watchdog timer reset count.
摘要翻译： 面向处理器的设备提供具有测试模式可编程复位的看门狗定时器。 当在定时器复位期间通过拉动测试模式硬件引脚将器件置于测试模式，然后向定时器提供适当的写入键，看门狗定时器复位计数可写入，允许看门狗的可编程持续时间 定时器复位。 看门狗定时器复位计数可以是由看门狗定时器复位计数器维持的复位持续时间值。 基于看门狗定时器测试模式使能逻辑和写入键的测试模式信号，看门狗定时器复位写使能逻辑使能写入看门狗定时器复位计数。
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7.发明授权UART character matching used for address matching on a register-by-register basis 失效UART字符匹配用于逐个寄存器的地址匹配
公开(公告)号：US6105081A
公开(公告)日：2000-08-15
申请号：US88610
申请日：1998-06-01
申请人： Melanie D. Typaldos
发明人： Melanie D. Typaldos
CPC分类号： G06F13/385
摘要： An asynchronous serial port is provided in a microcontroller that includes an address matching function that includes character matching functions such that incoming data is compared to match registers for special framing characters. Further, however, address bits are provided within the serial data, and additional matching bits are provided for matching those address bits along with the character data within the matching registers. In this way, not only is framing data detected by the detection of special characters, but a microcontroller can determine when it is being addressed in a multidrop, address bit protocol system by matching the address bit and address data.
摘要翻译： 在微控制器中提供异步串行端口，其包括包括字符匹配功能的地址匹配功能，使得将输入数据与特殊成帧字符的匹配寄存器进行比较。 然而，此外，还提供了串行数据内的地址位，并且提供了附加的匹配位，用于将这些地址位与匹配寄存器内的字符数据一起匹配。 以这种方式，不仅通过检测特殊字符检测到成帧数据，而且微控制器可以通过匹配地址位和地址数据来确定多点地址位协议系统何时被寻址。
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8.发明授权Emulator support mode for disabling and reconfiguring timeouts of a watchdog timer 失效仿真器支持模式，用于禁用和重新配置看门狗定时器的超时
公开(公告)号：US6145103A
公开(公告)日：2000-11-07
申请号：US56509
申请日：1998-04-07
CPC分类号： G06F11/3648
摘要： A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value. By monitoring a condition as the watchdog timer approaches its timeout value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register.
摘要翻译： 根据本发明的基于微控制器的设备提供具有用于禁用和重新配置超时的仿真器支持模式的看门狗定时器。 看门狗定时器处于仿真器支持模式时，看门狗定时器被禁止计数。 在公开的实施例中，通过使计数使能信号无效来禁止看门狗定时器计数。 因此，在仿真器支持模式期间可以防止发生看门狗超时。 此外，在仿真器支持模式下，看门狗定时器控制寄存器是可写的，允许仿真器禁用看门狗定时器，使能定时器或为定时器编程新的超时值。 无论定时器的使能位的状态如何，看门狗定时器控制寄存器都是可写的。 此外，在仿真器支持模式下，在写入键序列写入看门狗定时器控制寄存器之后，看门狗定时器当前计数在看门狗定时器控制寄存器之上的预定寄存器地址处可读写。 通过写入和读取预定的寄存器地址位置，仿真器能够定义和监视看门狗定时器接近其超时值的条件。 通过在看门狗定时器接近其超时值时监视条件，软件调试器可以在看门狗超时之前更好地预测和理解基于微控制器的器件的行为。 在公开的实施例中，通过看门狗定时器计数高位寄存器和看门狗定时器计数低寄存器，看门狗定时器当前计数是可读写的。
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9.发明授权System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver 失效具有接收数据寄存器的系统，用于存储指示异步串行接收器的状态的帧和状态位的至少九个数据位
公开(公告)号：US5958024A
公开(公告)日：1999-09-28
申请号：US920930
申请日：1997-08-29
CPC分类号： G06F13/385
摘要： An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.
摘要翻译： 具有控制寄存器和至少一个数据寄存器的异步串口与串行总线交换数据。 异步串行端口包括表示数据寄存器是否包含所有数据位的指示器，还是一些数据可能存储在控制寄存器中。 当接收到9位数据源（或具有多于8位数据的数据源）时，这些位不需要在多个寄存器之间划分，而是可以全部存储在接收数据寄存器中。 这在DMA期间或者当数据交换已被暂停时（例如通过中断）特别有用，而异步串行端口可以接收附加帧。 因为当扩展写位或扩展读位置1时，帧存储在单个寄存器中。 此外，接收数据寄存器还存储与接收数据相关联的状态位。 这在DMA操作中特别有用，当状态（包括奇偶校验，帧或超限错误）可以与检查存储的DMA数据本身的特定数据项相关联时。
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10.发明授权System for selecting between internal and external DMA request where ASP generates internal request is determined by at least one bit position within configuration register 失效用于在ASP生成内部请求的内部和外部DMA请求之间进行选择的系统由配置寄存器中的至少一个位位置决定
公开(公告)号：US5896549A
公开(公告)日：1999-04-20
申请号：US807103
申请日：1997-02-04
CPC分类号： G06F13/28
摘要： A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA). The microcontroller includes an execution unit, a DMA unit, one or more ASPs, and at least one input/output (I/O) pad formed upon a single monolithic semiconductor substrate. The execution unit is configured to execute instructions, preferably .times.86 instructions. Each ASP is configurable to generate an internal DMA request signal, which effectuates a DMA transfer of serial communication data, and multiple DMA control signals. Each I/O pad is adapted to receive an external DMA request signal generated by a device external to the microcontroller. The DMA unit includes selection logic coupled to one or more DMA channel circuits. The selection logic receives the internal and external DMA request signals as well as the DMA control signals, and produces a DMA request signal for each DMA channel circuit. Each DMA request signal is either an internal DMA request signal or an external DMA request signal, depending upon the DMA control signals. Each DMA channel circuit receives the corresponding DMA request signal and performs a data transfer operation in response to the DMA request signal. During the DMA transfer operation, data is read from a first address and written to a second address. Each ASP and DMA channel circuit includes at least one configuration register, the contents of which determine the operation of the ASP or DMA channel circuit.
摘要翻译： 提出了一种微控制器，其可配置为使用直接存储器访问（DMA）将数据传送到一个或多个异步串行端口（ASP）。 微控制器包括执行单元，DMA单元，一个或多个ASP以及形成在单个单片半导体衬底上的至少一个输入/输出（I / O）焊盘。 执行单元被配置为执行指令，优选地执行x86指令。 每个ASP可配置为产生内部DMA请求信号，从而实现串行通信数据的DMA传输和多个DMA控制信号。 每个I / O焊盘适于接收由微控制器外部的器件产生的外部DMA请求信号。 DMA单元包括耦合到一个或多个DMA通道电路的选择逻辑。 选择逻辑接收内部和外部DMA请求信号以及DMA控制信号，并为每个DMA通道电路产生DMA请求信号。 根据DMA控制信号，每个DMA请求信号是内部DMA请求信号或外部DMA请求信号。 每个DMA通道电路接收对应的DMA请求信号，并响应DMA请求信号执行数据传输操作。 在DMA传输操作期间，从第一地址读取数据并写入第二地址。 每个ASP和DMA通道电路包括至少一个配置寄存器，其内容决定了ASP或DMA通道电路的操作。
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