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公开(公告)号：US20240111702A1
公开(公告)日：2024-04-04
申请号：US17958111
申请日：2022-09-30
发明人： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
CPC分类号： G06F13/4045 , G06F13/24
摘要： A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.
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公开(公告)号：US20240231834A1
公开(公告)日：2024-07-11
申请号：US18133971
申请日：2023-04-12
发明人： Mark Rosenbluth , Rui Xu , Diane Orf , Michael Cotsford , Shreya Tekade , David Woods
IPC分类号： G06F9/4401
CPC分类号： G06F9/4403
摘要： A system includes a functional unit having a processor and address management circuitry. The address management circuitry is to receive a request from the processor, where the request is associated with a boot process initialized at the processor. The address management circuitry is to determine a bit stored at the address management circuitry has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process instead of a second node identifier associated with nodes storing physical locations associated with a memory address of the request. The address management circuitry can further transmit the request with the first node identifier to logic at a first node coupled to the memory region responsive to determining the bit has the first value.
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公开(公告)号：US12111779B2
公开(公告)日：2024-10-08
申请号：US17958229
申请日：2022-09-30
发明人： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
CPC分类号： G06F13/1668 , G06F13/4221 , G06F2213/0026
摘要： A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.
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公开(公告)号：US10942876B1
公开(公告)日：2021-03-09
申请号：US16683300
申请日：2019-11-14
发明人： Carl Ramey , Christopher Jackson , Diane Orf , Matt Orsini , Michael Cotsford , Mark B. Rosenbluth , Rui Xu
摘要： One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of the tiles.
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公开(公告)号：US20240231967A1
公开(公告)日：2024-07-11
申请号：US18094182
申请日：2023-01-06
发明人： Diane Orf , Mark Rosenbluth , Michael Cotsford , Rui Xu , Shreya Tekade
摘要： An integrated circuit includes a set of functional units having at least a first functional unit and a second functional unit. The first functional unit includes first processing circuitry and a first circuit coupled to the first processing circuitry to receive a message from the second functional unit of the set of functional units. The first circuit is further to delay the message for the first processing circuitry for a predetermined duration, where the predetermined duration is based in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit.
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公开(公告)号：US20240111694A1
公开(公告)日：2024-04-04
申请号：US17958229
申请日：2022-09-30
发明人： Rui Xu , Mark Rosenbluth , Diane Orf , Michael Cotsford , Shreya Tekade
CPC分类号： G06F13/1668 , G06F13/4221 , G06F2213/0026
摘要： A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.
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