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    Data cache virtual hint way prediction, and applications thereof
    1.
    发明授权
    Data cache virtual hint way prediction, and applications thereof 有权
    数据缓存虚拟提示方式预测及其应用

    公开(公告)号：US07594079B2

    公开(公告)日：2009-09-22

    申请号：US11545706

    申请日：2006-10-11

    Applicant: Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Vidya Rajagopalan

    Inventor： Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Vidya Rajagopalan

    IPC: G06F12/00

    CPC classification number: G06F12/0862 ,  G06F12/0864 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/6082

    Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

    Abstract translation: 一种基于虚拟提示的数据缓存方式预测方案及其应用。 在一个实施例中，处理器基于虚拟提示值或别名方式预测值从数据高速缓存中检索数据，并且在数据的物理地址可用之前将数据转发到依赖指令。 物理地址可用后，将物理地址与转发数据的物理地址标签值进行比较，以验证转发的数据是正确的数据。 如果转发的数据是正确的数据，则产生命中信号。 如果转发的数据不是正确的数据，则会产生未命中的信号。 任何对不正确数据进行操作的指令都将被无效和/或重播。

    Data cache virtual hint way prediction, and applications thereof
    3.
    发明申请
    Data cache virtual hint way prediction, and applications thereof 有权
    数据缓存虚拟提示方式预测及其应用

    公开(公告)号：US20080082721A1

    公开(公告)日：2008-04-03

    申请号：US11545706

    申请日：2006-10-11

    Applicant: Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Vidya Rajagopalan

    Inventor： Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Vidya Rajagopalan

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F12/0864 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/6082

    Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

    Abstract translation: 一种基于虚拟提示的数据缓存方式预测方案及其应用。 在一个实施例中，处理器基于虚拟提示值或别名方式预测值从数据高速缓存中检索数据，并且在数据的物理地址可用之前将数据转发到依赖指令。 物理地址可用后，将物理地址与转发数据的物理地址标签值进行比较，以验证转发的数据是正确的数据。 如果转发的数据是正确的数据，则产生命中信号。 如果转发的数据不是正确的数据，则会产生未命中信号。 任何对不正确数据进行操作的指令都将被无效和/或重播。

    Detection and prevention of write-after-write hazards, and applications thereof
    5.
    发明申请
    Detection and prevention of write-after-write hazards, and applications thereof 审中-公开
    检测和防止写后危害及其应用

    公开(公告)号：US20080082793A1

    公开(公告)日：2008-04-03

    申请号：US11529710

    申请日：2006-09-29

    Applicant: Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Karagada Ramarao Kishore

    Inventor： Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni ,  Karagada Ramarao Kishore

    IPC: G06F9/30

    CPC classification number: G06F9/3017 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

    Abstract: Apparatuses, systems, and methods for detecting and preventing write-after-write hazards, and applications thereof. In an embodiment, a load/store queue of a processor stores a first register destination value associated with a graduated load instruction. A graduation unit of the processor broadcasts a second register destination value associated with a graduating load instruction. Control logic coupled to the load/store queue and the graduation unit compares the first register destination value to the second register destination. If the first register destination value and the second register destination value match, the control logic prevents the graduated load instruction from altering an architectural state of the processor.

    Abstract translation: 用于检测和防止写后危害的设备，系统和方法及其应用。 在一个实施例中，处理器的加载/存储队列存储与刻度加载指令相关联的第一寄存器目的地值。 处理器的分度单元广播与刻度加载指令相关联的第二寄存器目的地值。 耦合到加载/存储队列和毕业单元的控制逻辑将第一寄存器目的地值与第二寄存器目的地进行比较。 如果第一寄存器目的地值和第二寄存器目标值匹配，则控制逻辑防止刻度加载指令改变处理器的架构状态。

    CACHE CONTROL TO REDUCE TRANSACTION ROLL BACK
    6.
    发明申请
    CACHE CONTROL TO REDUCE TRANSACTION ROLL BACK 有权
    CACHE控制减少交易回滚

    公开(公告)号：US20130297876A1

    公开(公告)日：2013-11-07

    申请号：US13461458

    申请日：2012-05-01

    Applicant: Meng-Bing Yu

    Inventor： Meng-Bing Yu

    IPC: G06F12/08

    CPC classification number: G06F12/122 ,  G06F9/467 ,  G06F12/126

    Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes a cache that is controlled by a cache controller. The cache controller is configured to replace cachelines in the cache based on a replacement scheme that prioritizes the replacement of cachelines that are less likely to cause roll back of a transaction of the microprocessor.

    Abstract translation: 在一个实施例中，提供微处理器。 微处理器包括由高速缓存控制器控制的高速缓存。 高速缓存控制器被配置为基于替换方案来替换高速缓存中的高速缓存行，所述替换方案优先考虑不太可能导致微处理器的事务的回滚的高速缓存行的替换。

    Integrated circuit with low output buffer energy consumption and related method
    7.
    发明授权
    Integrated circuit with low output buffer energy consumption and related method 失效
    具有低输出缓冲能耗的集成电路及相关方法

    公开(公告)号：US5604454A

    公开(公告)日：1997-02-18

    申请号：US536541

    申请日：1995-09-29

    Applicant: Jeffrey E. Maguire ,  Meng-Bing Yu

    Inventor： Jeffrey E. Maguire ,  Meng-Bing Yu

    IPC: H03K19/00 ,  H03B1/00

    CPC classification number: H03K19/0019

    Abstract: An integrated circuit (20) includes multiple output buffers (30, 50, 70) which switch substantially simultaneously. The output buffers (30, 50, 70) are connected together via a common node (25). Before any one of the output buffers (30, 50, 70) actively drives its corresponding output node to an appropriate logic state, a coupling circuit (42) in the output buffer (30) evaluates whether the new logic state matches the old logic state. If the coupling circuit (42) determines that the logic states are different, then it couples the output node to the common node (25). With each output buffer in the group of multiple output buffers (30, 50, 70) functioning similarly, energy is conserved by using the charge stored in the low-going nodes to charge up the high-going nodes.

    Abstract translation: 集成电路（20）包括基本同时切换的多个输出缓冲器（30,50,70）。 输出缓冲器（30,50,70）经由公共节点（25）连接在一起。 在任何一个输出缓冲器（30,50,70）有效地将其对应的输出节点驱动到适当的逻辑状态之前，输出缓冲器（30）中的耦合电路（42）评估新的逻辑状态是否与旧的逻辑状态相匹配 。 如果耦合电路（42）确定逻辑状态不同，则将输出节点耦合到公共节点（25）。 对于多个输出缓冲器组（30,50,70）中的每个输出缓冲器的功能相似，通过使用存储在低位节点中的电荷对高速节点进行充电来节省能量。

    Load/store unit for a processor, and applications thereof
    9.
    发明申请
    Load/store unit for a processor, and applications thereof 有权
    处理器的加载/存储单元及其应用

    公开(公告)号：US20080082794A1

    公开(公告)日：2008-04-03

    申请号：US11529728

    申请日：2006-09-29

    Applicant: Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni

    Inventor： Meng-Bing Yu ,  Era K. Nangia ,  Michael Ni

    IPC: G06F9/30

    CPC classification number: G06F9/3826 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    Abstract: A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

    Abstract translation: 处理器的加载/存储单元及其应用。 在一个实施例中，加载/存储单元包括被配置为存储与特定类别的指令相关联的信息和数据的加载/存储队列。 存储在加载/存储队列中的数据可以绕过依赖指令。 当属于特定类别的指令毕业生和指令与高速缓存未命中相关联的指令时，控制逻辑使指针存储在加载/存储分级缓冲器中，该加载/存储分级缓冲器指向与...相关联的加载/存储队列中的条目 指令。 加载/存储分级缓冲器确保分级指令以程序顺序访问加载/存储单元的共享资源。

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