公开(公告)号：US6121092A

公开(公告)日：2000-09-19

申请号：US243552

申请日：1999-02-02

申请人： Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0266

摘要： A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and silicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

摘要翻译： 半导体器件形成在具有ESD区域和内部区域的衬底上。 在ESD区域的一部分上形成保护层以防止硅化物的形成，并且在保护层未保护的内部和ESD区域的部分上形成硅化物。 保护层的一部分被去除，以将保护层的剩余部分形成为与包括在ESD区域中的栅电极相邻的侧壁间隔。

公开(公告)号：US06259140B1

公开(公告)日：2001-07-10

申请号：US09410360

申请日：1999-09-30

申请人： Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and suicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

摘要翻译： 半导体器件形成在具有ESD区域和内部区域的衬底上。 在ESD区域的一部分上形成保护层以防止硅化物的形成，并且在保护层未保护的内部和ESD区域的部分上形成硅化物。 保护层的一部分被去除，以将保护层的剩余部分形成为与包括在ESD区域中的栅电极相邻的侧壁间隔。

公开(公告)号：US06455898B1

公开(公告)日：2002-09-24

申请号：US09267303

申请日：1999-03-15

申请人： Meng-Hwang Liu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Meng-Hwang Liu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： An ESD protection structure for protecting an internal circuit comprising a primary protection device, a secondary protection device, and a substrate pickup is presented. The primary protection device and secondary protection device share a common source, and this common source implementation lowers the trigger voltage of the primary protection device to be about the same as the trigger voltage of the secondary protection device, thereby eliminating the need to use an isolation resistor between the primary and secondary protection devices.

摘要翻译： 提出了一种用于保护包括主保护装置，辅助保护装置和基板拾取器的内部电路的ESD保护结构。 主保护装置和次级保护装置共享共同的源头，这种常用的源实现将主保护装置的触发电压降低到与次级保护装置的触发电压大致相同，从而无需使用隔离 主保护和次级保护装置之间的电阻。

公开(公告)号：US6140682A

公开(公告)日：2000-10-31

申请号：US350480

申请日：1999-07-09

申请人： Meng-Hwang Liu ,  Chen-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Meng-Hwang Liu ,  Chen-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0266 ,  H01L2924/0002

摘要： A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to a standard cell layout and is adaptable for a variety of output driving specifications according to the need of a particular implementation. A doped region having a first conductivity type is formed in the substrate. A plurality of sets of cascode connected transistors having channels in the doped region is included. Sets of cascode connected transistors in the plurality include a first diffusion region, a second diffusion region on a first side of and separated from the first diffusion region by a channel of a first transistor, a third diffusion region on a second side of and separated from the first diffusion region by a channel of the second transistor, a fourth diffusion region on a first side of and separated from the second diffusion region by a channel of a third transistor, a fifth diffusion region on a second side of and separated from the third diffusion region by a channel of a fourth transistor. Gate structures are formed over the channels of the first, second, third and fourth transistors. An interconnect structure couples the first diffusion region to the contact pad, the fourth and fifth diffusion regions to the second supply terminal, the gate structures of the first and second transistors to a first supply terminal, the gate structure of the third transistor to a selected one of the second supply terminal and a signal source, and the gate structure of the fourth transistor to a selected one of the signal source and the second supply terminal. The structure acts typically as a pull-down stage for an output driver on an integrated circuit. A pull-up transistor is included in the complete circuit. The diffusion regions between the first and third transistor and between the second and fourth transistor are formed without silicide.

公开(公告)号：US5963808A

公开(公告)日：1999-10-05

申请号：US783995

申请日：1997-01-15

申请人： Wenpin Lu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

发明人： Wenpin Lu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7883

摘要： A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a column of floating gates on the dielectric; (3) forming an inhibit mask adjacent a first side of the column of floating gates; (4) implanting a dopant adjacent the first side and a second side of the column of floating gates, the first dopant having a second conductivity type opposite the first conductivity type; (5) forming a thermal oxide adjacent the first and second side of the column of floating gates such that the dopant adjacent the first side of the column is separated from the floating gates by the dielectric and the dopant adjacent the second side of the column is separated from the floating gates by a bird's beak encroachment of the thermal oxide formation; and (6) completing formation of control gate dielectric and control gates.

摘要翻译： 具有不对称的源极和漏极连接到具有Fowler-Nordheim隧道区域的掩埋位线的存储单元以及由每个单元上的鸟喙侵入限定的非隧穿区域。 一种非易失性半导体存储器件，包括单元的行和列排列，其中相邻列的单元共享单个位线。 一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成一列浮栅; （3）在所述浮栅的所述列的第一侧附近形成抑制掩模; （4）在所述浮栅的所述第一侧和所述第二侧附近注入掺杂剂，所述第一掺杂剂具有与所述第一导电类型相反的第二导电类型; （5）在浮置栅极列的第一和第二侧附近形成热氧化物，使得邻近该列的第一侧的掺杂剂通过电介质离开浮动栅极并且邻近该第二侧的掺杂剂是 通过鸟喙侵蚀热氧化物形成与浮动门分离; （6）完成控制栅介质和控制栅的形成。

公开(公告)号：US06269017B1

公开(公告)日：2001-07-31

申请号：US09262374

申请日：1999-03-04

申请人： Tao-Cheng Lu ,  Chung Ju Chen ,  Mam-Tsung Wang

发明人： Tao-Cheng Lu ,  Chung Ju Chen ,  Mam-Tsung Wang

IPC分类号： G11C1710

CPC分类号： G11C11/5692 ,  G11C17/12 ,  H01L27/112

摘要： Mask ROMS with fixed code implantation and associated integrated circuits are described. An integrated circuit has a Mask ROM including: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cell by a set of select lines, and the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column. The use of fixed code implantation results in a single current path during the reading of a given memory cell and permits the size of the corresponding device to be reduced and have better topography. The Mask ROM provides additional advantages because the use of the same select transistors for two banks reduces the overhead of select transistors for a given size of array, the use of only one sense amplifier per block reduces the overhead of sense amplifiers for a given size of array, and the use of odd and even word line decoders divides the memory cell array into a number of banks.

摘要翻译： 描述具有固定码植入和相关集成电路的掩模ROMS。 集成电路具有掩模ROM，该掩模ROM包括：包括第一存储单元组和第二存储单元组的存储单元阵列，以及通过一组选择线与第二存储单元组分离的第一存储单元组 并且所述第一存储单元组和所述第二存储单元组包括至少一个固定代码植入存储单元列。 在给定存储单元的读取期间，使用固定代码注入导致单个电流路径，并允许相应的器件的尺寸减小并具有更好的形貌。 掩模ROM提供了额外的优点，因为对于两个存储体使用相同的选择晶体管降低了给定尺寸阵列的选择晶体管的开销，每个块仅使用一个读出放大器减少了给定尺寸的读出放大器的开销 阵列，并且奇数和偶数字线解码器的使用将存储单元阵列划分成多个存储体。

公开(公告)号：US08952484B2

公开(公告)日：2015-02-10

申请号：US12949092

申请日：2010-11-18

申请人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L21/70 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/792 ,  H01L21/76232

摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.

摘要翻译： 提供了一种非易失性存储器及其制造方法。 非挥发性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。 栅极结构设置在基板上。 栅极结构包括电荷存储结构，栅极和间隔物。 电荷存储结构设置在基板上。 栅极设置在电荷存储结构上。 间隔件设置在栅极和电荷存储结构的侧壁上。 第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。 隔离结构分别设置在栅极结构的两侧的基板中。

公开(公告)号：US20120287539A1

公开(公告)日：2012-11-15

申请号：US13105270

申请日：2011-05-11

申请人： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection device electronically connected to a pad is provided. The ESD protection device includes K PNP transistors and a protection circuit, wherein K is a positive integer. An emitter of the 1st PNP transistor is electronically connected to the pad, a base of the ith PNP transistor is electronically connected to an emitter of the (i+1)th PNP transistor, and collectors of the K PNP transistors are electronically connected to a ground, wherein i is an integer and 1≦i≦(K−1). The protection circuit is electronically connected between a base of the Kth PNP transistor and the ground and provides a discharge path. An electrostatic signal from the pad is conducted to the ground through the discharge path and the K PNP transistors.

摘要翻译： 提供电连接到垫的静电放电（ESD）保护装置。 ESD保护装置包括K PNP晶体管和保护电路，其中K是正整数。 第一PNP晶体管的发射极电连接到焊盘，第i PNP晶体管的基极电连接到第（i + 1）PNP晶体管的发射极，并且K PNP晶体管的集电极电连接到 地面，其中i是整数，1＆nlE; i＆nlE;（K-1）。 保护电路电连接在第K PNP晶体管的基极与地之间并提供放电路径。 来自焊盘的静电信号通过放电路径和K PNP晶体管传导到地面。

公开(公告)号：US08203879B2

公开(公告)日：2012-06-19

申请号：US12834233

申请日：2010-07-12

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404

摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting a main voltage distribution group and a plurality of secondary voltage distribution groups, wherein each of the main voltage distribution group and the secondary voltage distribution groups includes N threshold-voltage distribution curves, and N is an integer greater than 2; selecting a first operation level and a second operation level according to a programming command; programming the first storage position according to the threshold-voltage distribution curve corresponding to the first operation level in the main voltage distribution group; selecting one of the secondary voltage distribution groups according to the first operation level and programming the second storage position according to the threshold-voltage distribution curve corresponding to the second operation level in the selected secondary voltage distribution group.

摘要翻译： 提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。 操作方法包括：设置主电压分配组和多个次级电压分布组，其中主电压分配组和次级电压分配组中的每一个包括N个阈值电压分布曲线，并且N是大于2的整数 ; 根据编程命令选择第一操作级别和第二操作级别; 根据与主电压分配组中的第一操作电平相对应的阈值电压分布曲线对第一存储位置进行编程; 根据第一操作电平选择二次电压分配组中的一个，并根据与所选次级电压分配组中的第二操作电平对应的阈值电压分布曲线对第二存储位置进行编程。

公开(公告)号：US08098522B2

公开(公告)日：2012-01-17

申请号：US12574093

申请日：2009-10-06

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/3468 ,  G11C16/0466 ,  G11C16/10

摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1≦i≦N.

摘要翻译： 提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。 操作方法包括：设置N个阈值电压分布曲线，其中N个阈值电压分布曲线对应于N个电平，N是大于2的整数; 当第一和第二存储位置被编程到第1和第N级时，分别根据第一阈值电压分布曲线和阈值电压辅助曲线将第一和第二存储位置编程到第一级和辅助级; 以及当所述第一和第二存储位置不被编程到所述第一和第N电平时，根据所述第i阈值电压分布曲线将所述第一和第二存储位置编程为第i级，其中i是整数和1＆nlE; 我＆nlE; N。