公开(公告)号：US20240312892A1

公开(公告)日：2024-09-19

申请号：US18534143

申请日：2023-12-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D Pendse

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/08155 ,  H01L2224/08225 ,  H01L2224/16157 ,  H01L2224/16227 ,  H01L2924/01029 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Apparatuses include a package substrate with package bonding pads and a die electrically coupled to the package substrate via conductive bonding elements. The die includes a first application-specific integrated circuit (ASIC) with first die input/output pads and a second ASIC with second die input/output pads. Each of the first die input/output pads is electrically coupled to at least one corresponding package bonding pad. At least one of the second die input/output pads is not electrically coupled to any package bonding pad, such that the second ASIC is left in an inoperable state.

公开(公告)号：US20240332275A1

公开(公告)日：2024-10-03

申请号：US18617009

申请日：2024-03-26

Applicant: Meta Platforms Technologies, LLC

Inventor： Jaesik Lee ,  Rajendra D Pendse

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/08145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: A multi-chiplet assembly may include a logic chiplet with an active frontside having first active circuitry. A multi-chiplet assembly may include a memory chiplet, electrically coupled to the logic chiplet, with an active frontside having second active circuitry. The active frontside of the logic chiplet may face a first direction, and the active frontside of the memory chiplet may face a second direction opposite the first direction. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US20240332252A1

公开(公告)日：2024-10-03

申请号：US18417411

申请日：2024-01-19

Applicant: Meta Platforms Technologies, LLC

Inventor： Jaspreet Singh Gandhi ,  Jaesik Lee ,  Rajendra D Pendse

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/4813 ,  H01L2224/48157 ,  H01L2224/73257 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/15311

Abstract: A multi-chiplet assembly may include a first logic chiplet. A multi-chiplet assembly may include a memory chiplet electrically coupled to the first logic chiplet. A multi-chiplet assembly may include a second logic chiplet. A multi-chiplet assembly may include a bridging chiplet electrically coupling the first logic chiplet to the second logic chiplet. Various other apparatuses, systems, and methods are also disclosed.