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公开(公告)号：US07165167B2
公开(公告)日：2007-01-16
申请号：US10458457
申请日：2003-06-10
IPC分类号： G06F9/24
CPC分类号： G06F9/3842 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3861
摘要： A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
摘要翻译： 微处理器可以包括被配置为发布操作的调度器和被配置为执行由调度器发出的存储器操作的加载存储单元。 加载存储单元被配置为存储识别发送到加载存储单元的存储器操作的信息。 响应于检测到所发出的存储器操作之一的不正确的数据推测，加载存储单元被配置为通过向调度器提供指示来重播所发布的存储器操作中的至少一个。 调度器被配置为响应地重新发出由加载存储单元识别的存储器操作。
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公开(公告)号：US07251710B1
公开(公告)日：2007-07-31
申请号：US10755734
申请日：2004-01-12
IPC分类号： G06F13/00
CPC分类号： G06F12/0877 , G06F12/0862 , G06F12/0891 , G06F12/0897 , G06F12/126
摘要： A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.
摘要翻译： 包括固定等待时间读/写流水线的缓存存储器子系统。 高速缓冲存储器子系统包括高速缓存存储器，其可以被配置为存储多条高速缓存数据行。 高速缓存存储器子系统还包括调度器，其可以被配置为使用固定的等待时间流水线调度与高速缓存存储器相关联的信息的读取和写入。 响应于调度读取请求，调度器可以被进一步配置为在读取请求的调度之后使相关联的写入发生固定数量的周期。
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3.发明授权System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor 有权用于防止操作中的飞行中实例在数据推测微处理器内中断操作重放的系统和方法公开(公告)号：US07363470B2
公开(公告)日：2008-04-22
申请号：US10429082
申请日：2003-05-02
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/383 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A microprocessor may include one or more functional units configured to execute operations, a scheduler configured to issue operations to the functional units for execution, and at least one replay detection unit. The scheduler may be configured to maintain state information for each operation. Such state information may, among other things, indicate whether an associated operation has completed execution. The replay detection unit may be configured to detect that one of the operations in the scheduler should be replayed. If an instance of that operation is currently being executed by one of the functional units when operation is detected as needing to be replayed, the replay detection unit is configured to inhibit an update to the state information for that operation in response to execution of the in-flight instance of the operation. Various embodiments of computer systems may include such a microprocessor.
摘要翻译： 微处理器可以包括被配置为执行操作的一个或多个功能单元，被配置为向功能单元发布操作的调度器以及至少一个重放检测单元。 调度器可以被配置为维护每个操作的状态信息。 这样的状态信息可以指示关联的操作是否已经完成执行。 重放检测单元可以被配置为检测应该重播调度器中的一个操作。 如果当检测到需要重播的操作时，当该功能单元的一个当前正在执行该操作的实例时，重放检测单元被配置为响应于执行该操作而禁止对该操作的状态信息的更新 -flight实例的操作。 计算机系统的各种实施例可以包括这样的微处理器。
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4.发明授权System and method for handling exceptional instructions in a trace cache based processor 有权用于处理基于跟踪缓存的处理器中的异常指令的系统和方法公开(公告)号：US07133969B2
公开(公告)日：2006-11-07
申请号：US10676437
申请日：2003-10-01
申请人： Mitchell Alsup , Gregory William Smaus , James K. Pickett , Brian D. McMinn , Michael A. Filippo , Benjamin T. Sander
发明人： Mitchell Alsup , Gregory William Smaus , James K. Pickett , Brian D. McMinn , Michael A. Filippo , Benjamin T. Sander
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3861 , G06F12/0875
摘要： A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.
摘要翻译： 系统可以包括指令高速缓存，包括多个跟踪高速缓存条目的跟踪高速缓存以及耦合到指令高速缓存和跟踪高速缓存的跟踪发生器。 跟踪发生器可以被配置为接收由指令高速缓存输出的一组指令，用于存储在多个跟踪高速缓存条目之一中。 跟踪发生器可以被配置为检测指令组内的异常指令，并且防止异常指令被存储在多个跟踪高速缓存条目中的相同的一个跟踪高速缓存条目中，如任何非异常指令。
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5.发明授权Speculation pointers to identify data-speculative operations in microprocessor 有权用于识别微处理器中数据推测操作的推测指针公开(公告)号：US07266673B2
公开(公告)日：2007-09-04
申请号：US10429159
申请日：2003-05-02
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3865
摘要： A microprocessor may include a retire queue and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation pointer identifying outstanding operations on which data speculation has been verified by that data speculation verification unit. The retire queue is configured to selectively retire operations dependent on the speculation pointer received from each of the data speculation verification units.
摘要翻译： 微处理器可以包括退出队列和一个或多个数据推测验证单元。 数据推测验证单元被配置为验证对操作执行的数据推测。 每个数据推测验证单元产生识别由该数据推测验证单元已经对其进行数据猜测的未完成操作的各个推测指针。 退休队列被配置为根据从每个数据推测验证单元接收的推测指针选择性地退出操作。
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6.发明授权Controlling writes to non-renamed register space in an out-of-order execution microprocessor 有权控制对无序执行微处理器中的未重命名寄存器空间的写入公开(公告)号：US07373484B1
公开(公告)日：2008-05-13
申请号：US10755692
申请日：2004-01-12
申请人： Arun Radhakrishnan , Benjamin T. Sander , Michael A. Filippo , Michael T. Clark , David E. Kroesche
发明人： Arun Radhakrishnan , Benjamin T. Sander , Michael A. Filippo , Michael T. Clark , David E. Kroesche
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3013 , G06F9/384
摘要： A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.
摘要翻译： 控制对未重新命名的寄存器空间的写入操作的方法包括：接收对非重命名寄存器空间内的给定寄存器的写操作。 该方法还包括确定是否存在对给定寄存器的挂起写入操作。 响应于确定对给定寄存器的挂起写入操作存在，该方法包括阻止对给定寄存器的写入操作被调度。 然而，响应于确定对给定寄存器的挂起写操作不存在，该方法包括允许对给定寄存器的写操作进行调度。 此外，如果对给定寄存器的挂起写入操作不存在，则该方法包括允许对未重新命名的寄存器空间内的不同寄存器的后续写入操作进行调度。
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7.发明授权Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy 有权预取单元，用于缓存存储器层次结构的高速缓存存储器子系统公开(公告)号：US07836259B1
公开(公告)日：2010-11-16
申请号：US10817693
申请日：2004-04-02
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A prefetch unit for use with a cache subsystem. The prefetch unit includes a stream storage coupled to a prefetch unit. The stream storage may include a plurality of locations configured to store a plurality of entries each corresponding to a respective range of prefetch addresses. The prefetch control may be configured to prefetch an address in response to receiving a cache access request including an address that is within the respective range of prefetch addresses of any of the plurality of entries.
摘要翻译： 用于缓存子系统的预取单元。 预取单元包括耦合到预取单元的流存储器。 流存储器可以包括被配置为存储多个条目的多个位置，每个条目对应于预取地址的相应范围。 预取控制可以被配置为响应于接收包括在多个条目中的任何一个的预取地址的相应范围内的地址的高速缓存访问请求来预取地址。
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8.发明授权Processor with dependence mechanism to predict whether a load is dependent on older store 有权具有依赖机制的处理器来预测负载是否依赖于较旧的存储公开(公告)号：US07415597B2
公开(公告)日：2008-08-19
申请号：US10936296
申请日：2004-09-08
CPC分类号： G06F9/3842 , G06F9/3455 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3838
摘要： A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
摘要翻译： 处理器可以包括被配置为发布操作的调度器和被配置为执行由调度器发出的存储器操作的加载存储单元。 加载存储单元被配置为存储识别发送到加载存储单元的存储器操作的信息。 响应于检测到所发出的存储器操作之一的不正确的数据推测，加载存储单元被配置为通过向调度器提供指示来重播所发布的存储器操作中的至少一个。 调度器被配置为响应地重新发出由加载存储单元识别的存储器操作。
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公开(公告)号：US07321964B2
公开(公告)日：2008-01-22
申请号：US10615101
申请日：2003-07-08
CPC分类号： G06F9/30043 , G06F9/3834
摘要： A microprocessor may include a dispatch unit configured to dispatch load and store operations and a load store unit configured to store information associated with load and store operations dispatched by the dispatch unit. The load store unit includes a STLF (Store-to-Load Forwarding) buffer that includes a plurality of entries. The load store unit is configured to generate an index dependent on at least a portion of an address of a load operation, to use the index to select one of the plurality of entries, and to forward data included in the one of the plurality of entries as a result of the load operation.
摘要翻译： 微处理器可以包括配置成调度加载和存储操作的调度单元和被配置为存储与调度单元调度的加载和存储操作相关联的信息的加载存储单元。 加载存储单元包括包括多个条目的STLF（存储到负载转发）缓冲器。 加载存储单元被配置为生成依赖于加载操作的地址的至少一部分的索引，以使用索引来选择多个条目中的一个，并且转发包括在多个条目中的一个条目中的数据 作为加载操作的结果。
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10.发明授权Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor 有权用于在处理器中具有问题锁定机构的独立可调度功能单元的装置和方法公开(公告)号：US06944744B2
公开(公告)日：2005-09-13
申请号：US10228929
申请日：2002-08-27
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3885
摘要： A functional unit of a processor may be configured to operate on instructions as either a single, wide functional unit or as multiple, independent narrower units. For example, an execution unit may be scheduled to execute an instruction as a single double-wide execution unit or as two independently schedulable single-wide execution units. Functional unit portions may be independently schedulable for execution of instructions operating on a first data type (e.g. SISD instructions). For single-wide instructions, functional unit portions may be scheduled independently. An issue lock mechanism may lock functional unit portions together so that they form a single multi-wide functional unit. For certain multi-wide instructions (e.g. certain SIMD instructions), an instruction operating on a multi-wide or vector data type may be scheduled so that the full multi-wide operation is performed concurrently by functional unit portions locked together as a one wide functional unit.
摘要翻译： 处理器的功能单元可以被配置为作为单个，宽功能单元或多个独立的较窄单元的指令进行操作。 例如，可以将执行单元调度为执行作为单个双宽执行单元的指令或作为两个可独立调度的单宽执行单元执行。 功能单元部分可以是独立可调度的，用于执行基于第一数据类型（例如SISD指令）的指令。 对于单宽指令，可以独立地调度功能单元部分。 问题锁定机构可以将功能单元部分锁定在一起，使得它们形成单个多宽度功能单元。 对于某些多宽指令（例如某些SIMD指令），可以调度在多宽或向量数据类型上操作的指令，使得全功能多操作由作为一个宽功能的锁定在一起的功能单元部分同时执行 单元。
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