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1.发明授权Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization 有权使用二维瓦片和交替箱体进行光栅化，以提高渲染利用率公开(公告)号：US06803916B2
公开(公告)日：2004-10-12
申请号：US09861475
申请日：2001-05-18
申请人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
发明人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
IPC分类号： G06T120
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
摘要翻译： 公开了一种用于光栅化和渲染图形数据的系统和方法。 顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。 可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。 由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。 然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。
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公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译： 图形系统包括帧缓冲器，写地址生成器和像素缓冲器。 从帧缓冲器接收到的像素突发可能不是显示顺序。 在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。 写入地址对应于每个相应像素的突发内的相对显示顺序。 突发中的每个像素被存储到像素缓冲器中的其写入地址。 这样，突发中的像素以像素缓冲器内的显示顺序存储。
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公开(公告)号：US07027064B2
公开(公告)日：2006-04-11
申请号：US10086174
申请日：2002-02-28
CPC分类号： G09G5/39 , G06F12/0804 , G06F12/0897 , G06F12/126 , G06F2212/455 , G06T1/60 , G09G2360/121
摘要： An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.
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公开(公告)号：US06720969B2
公开(公告)日：2004-04-13
申请号：US09861172
申请日：2001-05-18
IPC分类号： G09G536
CPC分类号： G06F12/0897 , G06T1/60 , G06T15/005 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/122 , Y02D10/13
摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
摘要翻译： 描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。 该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。 在空的存储器循环期间提供了周期性的一级缓存块清理。
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公开(公告)号：US06812929B2
公开(公告)日：2004-11-02
申请号：US10094957
申请日：2002-03-11
IPC分类号： G06F1318
CPC分类号： G09G5/39 , G09G5/363 , G09G2360/121
摘要： A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.
摘要翻译： 图形系统可以包括帧缓冲器，其包括若干组一个或多个存储器组和高速缓存。 响应于接收到高速缓存填充请求，帧缓冲器可以将数据从一个存储体加载到高速缓存中。 每组存储体可以独立于彼此的存储体组来访问。 耦合到帧缓冲器的帧缓冲器接口包括多个高速缓存填充请求队列。 每个高速缓存填充请求队列被配置为存储一个或多个缓存填充请求，其针对存储器组的相应组之一。 帧缓冲器接口被配置为从缓存填充请求队列中的一个选择高速缓存填充请求，所述缓存填充请求队列存储针对当前未被访问的一组存储器组的高速缓存填充请求，并且向帧缓冲器提供所选择的高速缓存填充请求。
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公开(公告)号：US06778179B2
公开(公告)日：2004-08-17
申请号：US09970113
申请日：2001-10-03
IPC分类号： G09G536
CPC分类号： G06F12/0897 , G06T1/60 , G06T15/005 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/122 , Y02D10/13
摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
摘要翻译： 描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。 该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。 在空的存储器循环期间提供了周期性的一级缓存块清理。
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公开(公告)号：US06895458B2
公开(公告)日：2005-05-17
申请号：US10090491
申请日：2002-03-04
申请人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
发明人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
CPC分类号： G09G5/363 , G06F13/36 , G06T15/005
摘要： A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.
摘要翻译： 一种用于管理主单元和从单元之间的双向数据总线的控制的系统。 主机通过请求操作码总线，应答操作码总线和数据总线耦合到从机。 如果主机处于总线驱动状态（相对于数据总线）并接收到读取请求，则主机放弃总线控制并通过请求操作码总线发送读取请求。 从单元假设总线控制，并通过数据总线发送所请求的数据。 如果主机处于总线感测状态并接收写请求，则主机通过请求操作码总线向从机发送最后一个读操作码，并等待从机通过应答操作码总线返回特殊令牌。 在接收到特殊令牌时，主单元承担总线控制并执行写入事务。
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8.发明授权System and method for handling display device requests for display data from a frame buffer 有权用于处理从帧缓冲器显示数据的显示设备请求的系统和方法公开(公告)号：US06806883B2
公开(公告)日：2004-10-19
申请号：US10094930
申请日：2002-03-11
申请人： Michael G. Lavelle , Yan Yan Tang
发明人： Michael G. Lavelle , Yan Yan Tang
IPC分类号： G06F1318
摘要： A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.
摘要翻译： 图形系统可以包括帧缓冲器，耦合到访问帧缓冲器中的数据的处理设备，耦合到帧缓冲器的帧缓冲器接口，以及输出控制器，被配置为断言显示数据的请求以提供给显示设备。 帧缓冲器接口可以从输出控制器接收对显示数据的请求，并且如果处理设备正在请求访问由显示数据请求所针对的帧缓冲区的一部分，则向帧缓冲器提供对显示数据的请求的延迟。 例如，如果帧缓冲器包括多个存储体并且显示数据的请求针对第一存储体，则如果处理设备正在请求访问第一存储体，则帧缓冲器接口可以延迟向帧缓冲器提供对显示数据的请求 。
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9.发明授权公开(公告)号：US08134570B1
公开(公告)日：2012-03-13
申请号：US11532779
申请日：2006-09-18
申请人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
发明人： Jerome F. Duluk, Jr. , Andrew J. Tao , Roger L. Allen , Svetoslav D. Tzvetkov , Yan Yan Tang , Elena M. Ing
IPC分类号： G09G5/00
CPC分类号： G06T15/005
摘要： A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.
摘要翻译： 提供了用于打包图形属性的系统，方法和计算机程序产品。 在使用中，识别出多个图形属性。 打包这样的图形属性，使得打包的图形属性能够利用像素着色器进行处理。
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公开(公告)号：US20110078689A1
公开(公告)日：2011-03-31
申请号：US12890518
申请日：2010-09-24
IPC分类号： G06F9/46
CPC分类号： G06F12/0284 , G06F9/3851 , G06F12/0607
摘要： A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.
摘要翻译： 一种并行线程处理器中线程地址映射的方法。 该方法包括接收与线程组中的第一线程相关联的线程地址; 基于线程地址在线程地址空间的本地窗口内的位置来计算有效地址; 基于有效地址和与第一线程相关联的线程标识符计算与线程组相关联的地址空间中的线程组地址; 以及基于所述线程组地址和线程组标识符计算与所述第一线程相关联的虚拟地址，其中所述虚拟地址用于访问与所述线程地址相关联的存储器中的位置以加载或存储数据。
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