公开(公告)号：US20100003414A1

公开(公告)日：2010-01-07

申请号：US12465668

申请日：2009-05-14

申请人： Michael E. Reed ,  David E. Reed ,  Dale Collins

发明人： Michael E. Reed ,  David E. Reed ,  Dale Collins

IPC分类号： B05D7/06 ,  B05D5/00 ,  B05D3/00

CPC分类号： B05B14/40

摘要： A spray box assembly including, in combination, a top spray box, a bottom spray box, the boxes being juxtapositioned to define a pathway therebetween, at least one spray assembly positioned within at least one of the boxes and a supply assembly for supplying a treating solution to the spray assembly to coat product with the treating solution as the product is fed through the pathway and also including a method of coating a product with a treating solution, comprising the steps of feeding the product into a pathway between top spray box and a bottom spray box and spraying the treating solution within at least one of the boxes about the pathway to coat the product with the treating solution as the product is fed through the pathway.

摘要翻译： 一种喷雾箱组件，其组合包括顶部喷雾箱，底部喷雾箱，所述盒并置以在其间限定通道，至少一个位于至少一个盒子内的喷洒组件和用于供应处理 该溶液在产品通过该通道进料时，与处理溶液一起涂覆产品，还包括用处理溶液涂覆产品的方法，该方法包括以下步骤：将产物进料到顶部喷雾盒和 底部喷雾箱，并且当处理溶液通过该通道进料时，将处理溶液喷洒在围绕通路的至少一个盒中，以用处理溶液涂覆产品。

公开(公告)号：US07534299B2

公开(公告)日：2009-05-19

申请号：US11018517

申请日：2004-12-20

申请人： Michael E. Reed ,  David E. Reed ,  Dale Collins

发明人： Michael E. Reed ,  David E. Reed ,  Dale Collins

IPC分类号： B05B13/06 ,  B05B1/28

CPC分类号： B05B14/40 ,  Y02P70/36

摘要： A spray box assembly including, in combination, a top spray box, a bottom spray box, the boxes being juxtapositioned to define a pathway therebetween, at least one spray assembly positioned within at least one of the boxes and a supply assembly for supplying a treating solution to the spray assembly to coat product with the treating solution as the product is fed through the pathway and also including a method of coating a product with a treating solution, comprising the steps of feeding the product into a pathway between top spray box and a bottom spray box and spraying the treating solution within at least one of the boxes about the pathway to coat the product with the treating solution as the product is fed through the pathway.

摘要翻译： 一种喷雾箱组件，其组合包括顶部喷雾箱，底部喷雾箱，所述盒并置以在其间限定通道，至少一个位于至少一个盒子内的喷洒组件和用于供应处理 该溶液在产品通过该通道进料时，与处理溶液一起涂覆产品，还包括用处理溶液涂覆产品的方法，该方法包括以下步骤：将产物进料到顶部喷雾盒和 底部喷雾箱，并且当处理溶液通过该通道进料时，将处理溶液喷洒在围绕通路的至少一个盒中，以用处理溶液涂覆产品。

公开(公告)号：US06078444A

公开(公告)日：2000-06-20

申请号：US634161

申请日：1996-04-18

申请人： G. Diwakar Vishakhadatta ,  David E. Reed ,  Jerrell P. Hein ,  G. Tyson Tuttle

发明人： G. Diwakar Vishakhadatta ,  David E. Reed ,  Jerrell P. Hein ,  G. Tyson Tuttle

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B5/55 ,  G11B5/58 ,  G11B5/596 ,  G11B19/28 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B5/00 ,  H03M1/12

CPC分类号： G11B5/012 ,  G11B19/28 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/1403 ,  G11B5/09 ,  G11B5/5526 ,  G11B5/553 ,  G11B5/5547 ,  G11B5/58 ,  G11B5/59605 ,  G11B5/59622 ,  G11B5/59633 ,  G11B5/59688 ,  G11B20/1258 ,  G11B5/5534 ,  G11B5/5965

摘要： A circuit is provided for use with analog to digital conversion techniques in sampled amplitude read channel integrated circuits. A common ADC may be utilized for conversion of both high frequency disk data such as user data and servo data, for example, and for low frequency auxiliary data such as, for example, motor back-EMF current signals. The ADC may utilize the relatively low bit accuracy required for the read channel disk data and through oversampling techniques obtain sufficient conversion accuracy to meet the relatively higher precision requirements for the auxiliary data conversion. The auxiliary data is modified by a ramp signal and the ADC is run on a clock generated from a dithered frequency source so that ADC quantization errors may be randomized.

摘要翻译： 在采样幅度读通道集成电路中提供用于模数转换技术的电路。 例如，可以使用公共ADC来转换诸如用户数据和伺服数据的高频盘数据，以及用于低频辅助数据，例如电动机反电动势电流信号。 ADC可以利用读通道盘数据所需的相对较低的位精度，并且通过过采样技术获得足够的转换精度以满足对辅助数据转换的相对较高的精度要求。 辅助数据由斜坡信号修改，ADC在从抖动频率源产生的时钟上运行，因此ADC量化误差可以随机化。

公开(公告)号：US6028728A

公开(公告)日：2000-02-22

申请号：US7082

申请日：1998-01-14

申请人： David E. Reed

发明人： David E. Reed

IPC分类号： G11B5/012 ,  G11B20/10 ,  G11B20/14 ,  G11B5/09

CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/1426 ,  G11B5/012

摘要： A sub-baud rate write circuit is disclosed which writes RLL encoded channel data to a disk storage medium using a write clock frequency significantly below the baud rate. This allows for a higher channel data rate without increasing the cost and complexity of the write circuitry. The write circuitry operates by re-encoding the RLL encoded channel data according to a particular mapping to generate write data at the write clock rate, and then writing the write data to the disk at appropriate phase delays. The phase delays are generated by passing the write clock through an array of delay circuits. The resulting write signal is the same as if the RLL encoded data were written to the disk using a baud rate write clock. The write circuitry of the present invention is ideally suited for use in a sub-sampled read/write channel where the object is to reduce the cost and complexity by clocking the entire channel at a frequency significantly below the baud rate.

摘要翻译： 公开了一种子波特率写入电路，其使用明显低于波特率的写入时钟频率将RLL编码的信道数据写入到磁盘存储介质。 这允许更高的信道数据速率，而不增加写入电路的成本和复杂性。 写电路通过根据特定映射对RLL编码的信道数据进行重新编码，以写入时钟速率生成写入数据，然后以适当的相位延迟将写入数据写入到盘来进行操作。 通过将写入时钟通过延迟电路阵列来产生相位延迟。 所产生的写入信号与使用波特率写入时钟将RLL编码数据写入磁盘的写入信号相同。 本发明的写入电路理想地适用于子采样读/写通道，其中目的是通过以大大低于波特率的频率对整个通道进行定时来降低成本和复杂性。

公开(公告)号：US5862161A

公开(公告)日：1999-01-19

申请号：US697694

申请日：1996-08-28

申请人： David E. Reed ,  Richard T. Behrens

发明人： David E. Reed ,  Richard T. Behrens

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/6343 ,  G11B20/10277 ,  H03M13/41 ,  H03M5/145 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/10175 ,  G11B20/1426 ,  G11B2220/2516

摘要： This invention provides apparatus for reliably and efficiently reading data from a magnetic storage medium under the condition that adjacent magnetization regions are partially erased. A simplified nonlinear description of a read signal resulting from such partially erased magnetization regions is used to derive a state machine model of the read signal. The state machine model implicitly defines a sequence detector for demodulating recorded data from received samples. For a PR4 signal, the state machine has ten states; for an EPR4 signal, the state machine has eighteen states; and for an EEPR4 signal, the state machine has twenty-six states. The PR4 machine is further simplified using squaring and state sharing to provide state machine models with six and four states.

摘要翻译： 本发明提供了在相邻磁化区域被部分擦除的条件下可靠且有效地从磁存储介质读取数据的装置。 使用由这种部分擦除的磁化区域产生的读取信号的简化的非线性描述来导出读取信号的状态机器模型。 状态机模型隐含地定义用于解调来自接收样本的记录数据的序列检测器。 对于PR4信号，状态机有十个状态; 对于EPR4信号，状态机有十八个状态; 对于EEPR4信号，状态机有二十六个状态。 PR4机器使用平方和状态共享进一步简化，以提供具有六个和四个状态的状态机模型。

公开(公告)号：US5726818A

公开(公告)日：1998-03-10

申请号：US567681

申请日：1995-12-05

申请人： David E. Reed ,  William G. Bliss

发明人： David E. Reed ,  William G. Bliss

IPC分类号： G11B5/596 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B21/10 ,  H04L7/02

CPC分类号： H04L7/0029 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/1403 ,  G11B5/09 ,  H04L7/0062 ,  G11B20/1258 ,  G11B2020/10888 ,  G11B2020/1234 ,  G11B2020/1282 ,  H04L2007/047 ,  H04L7/0004

摘要： A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.

摘要翻译： 采样幅度读取通道通过从离散时间内插样本值的序列中检测数字数据来读取存储在磁性介质上的用户数据和嵌入式伺服数据。 写入频率合成器产生写入时钟，用于以预定波特率向所选择的区域向磁性介质写入数字数据，并且在读回时，读取频率合成器以略高于写入频率的频率产生固定采样时钟 外部区域。 采样设备以固定采样率对数据区和伺服楔进行采样，以产生不与波特率同步的离散时间通道采样序列。 在采样之前，模拟接收滤波器处理读取信号以衰减混叠噪声，而不必在数据区或伺服楔上调整其频谱。 离散时间均衡滤波器根据预定的部分响应（PR4，EPR4，EEPR4等）均衡信道样本。 内插定时恢复电路响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。 定时恢复电路还产生用于计时离散时间序列检测器和脉冲检测器的同步数据时钟，其从内插样本值检测数字用户和伺服数据。

公开(公告)号：US06980039B1

公开(公告)日：2005-12-27

申请号：US10792486

申请日：2004-03-03

申请人： David Dening ,  David E. Reed ,  Baker Scott

发明人： David Dening ,  David E. Reed ,  Baker Scott

IPC分类号： H02M3/156 ,  H03K3/84

CPC分类号： H02M1/12 ,  H02M3/156

摘要： A DC—DC converter includes a variable frequency oscillator, a control system and a power train. The DC—DC converter is well suited for use in a cell phone. The control system uses the output of the oscillator to control the power train. The oscillator varies its frequency as a function of a pseudo random number generator, thereby reducing electromagnetic interference caused by ripple in the output of the DC—DC converter.

摘要翻译： DC-DC转换器包括可变频率振荡器，控制系统和传动系。 DC-DC转换器非常适用于手机。 控制系统使用振荡器的输出来控制传动系。 振荡器根据伪随机数发生器改变其频率，从而减少由DC-DC转换器的输出中的纹波引起的电磁干扰。

公开(公告)号：US06819514B1

公开(公告)日：2004-11-16

申请号：US08640351

申请日：1996-04-30

申请人： Richard T. Behrens ,  Li Du ,  William G. Bliss ,  David E. Reed ,  Mark S. Spurbeck

发明人： Richard T. Behrens ,  Li Du ,  William G. Bliss ,  David E. Reed ,  Mark S. Spurbeck

IPC分类号： G11B5035

CPC分类号： G11B20/10194 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/1258 ,  G11B20/1876

摘要： A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

摘要翻译： 用于磁盘记录的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步采样值检测数字数据 公开了使用维特比序列检测器。 为了最小化来自定时和增益控制环路的干扰，使用最佳正交投影操作将自适应均衡器滤波器的相位和幅度响应约束在预定频率，作为对最小均方（LMS）适配算法的修改。 此外，通过内插定时恢复，均衡器滤波器及其相关等待时间从定时恢复环路中移除，从而允许较高阶离散时间滤波器和较低阶模拟滤波器。

公开(公告)号：US06246723B1

公开(公告)日：2001-06-12

申请号：US09072285

申请日：1998-05-04

申请人： William G. Bliss ,  David E. Reed ,  Marvin L. Vis ,  German S. Feyh

发明人： William G. Bliss ,  David E. Reed ,  Marvin L. Vis ,  German S. Feyh

IPC分类号： H04L512

CPC分类号： G11B20/10009 ,  G11B20/10055 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6343 ,  H04L1/0054

摘要： A sampled amplitude read channel is disclosed for disc storage systems that extracts early-decisions from a discrete-time trellis sequence detector to generate estimated target values for use in decision-directed timing recovery, gain control, and adaptive equalization. The trellis sequence detector comprises a metric generator for generating error metrics corresponding to a plurality of states of a state transition diagram, and a plurality of path memories which correspond to the paths of a trellis. The path memories store a plurality of survivor sequences which eventually merge into a most likely sequence at the output of the path memories. To reduce the latency in generating the estimated target samples, the trellis sequence detector outputs an early-decision from an intermediate location within the path memories. The early-decision is then converted into the partial response signaling space of the read signal samples. To improve the accuracy in estimating the target sample values, the accumulated metrics of a predetermined number of states are compared and the early-decision value is selected from the path memory having the smallest error metric. Alternatively, a majority-vote circuit evaluates the intermediate values stored in a predetermined number of the path memories and outputs the intermediate value that occurs most frequently. Although the early-decision technique of the present invention requires more latency than a simple slicer circuit, during acquisition the estimated target sample values are not used and therefore the increase in latency is not a significant problem.

摘要翻译： 公开了用于从离散时间网格序列检测器提取早期决定以产生用于决策定时恢复，增益控制和自适应均衡的估计目标值的盘存储系统的采样幅度读取信道。 网格序列检测器包括用于产生与状态转移图的多个状态相对应的误差度量的度量发生器，以及对应于网格的路径的多个路径存储器。 路径存储器存储多个幸存者序列，其最终在路径存储器的输出处合并成最可能的序列。 为了减少生成估计的目标样本的延迟，网格序列检测器从路径存储器内的中间位置输出早期决定。 然后将早期决定转换为读取信号样本的部分响应信令空间。 为了提高估计目标采样值的准确性，比较预定数量状态的累积度量，并从具有最小误差度量的路径存储器中选择早期判定值。 或者，多数投票电路评估存储在预定数量的路径存储器中的中间值，并输出最频繁出现的中间值。 虽然本发明的早期决策技术比简单的限幅器电路需要更多的延迟，但在采集期间，不使用估计的目标采样值，因此等待时间的增加不是一个显着的问题。

公开(公告)号：US6023386A

公开(公告)日：2000-02-08

申请号：US961727

申请日：1997-10-31

申请人： David E. Reed ,  William G. Bliss

发明人： David E. Reed ,  William G. Bliss

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B27/30

CPC分类号： G11B20/10055 ,  G11B20/10037 ,  G11B20/1403 ,  G11B27/3027 ,  G11B5/09 ,  G11B20/10009

摘要： In a magnetic disk storage system, a sampled amplitude read channel is disclosed that employs a fault tolerant sync mark detector for detecting a sync mark from the channel samples in order to synchronize a time varying sequence detector. The read channel preferably employs PR4 equalization for timing recovery and gain control, and EEPR4 equalization for sequence detection. The EEPR4 sequence detector operates according to a time varying state machine matched to a predetermined trellis code constraint. Because the state machine is time varying, the data stream must be synchronized at the input of the sequence detector rather than at the output as in the prior art. The present invention provides a fault tolerant sync mark detector that detects a sync mark from the EEPR4 channel samples before being input into the sequence detector. In one embodiment, the sync mark detector accumulates a squared error between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the accumulated squared error is less than a predetermined lower threshold. In an alternative embodiment, the sync mark detector computes a correlation between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the correlation is greater than a predetermined upper threshold. The correlation sync mark detector is the preferred embodiment because it is insensitive to d.c. offsets, it exhibits excellent performance in detecting short sync marks, and it can be implemented as two cascaded finite impulse response filters without requiring multipliers or squarers.

摘要翻译： 在磁盘存储系统中，公开了一种采样幅度读取通道，其采用容错同步标记检测器来检测来自信道样本的同步标记，以便使时变序列检测器同步。 读通道优选采用PR4均衡来进行定时恢复和增益控制，以及用于序列检测的EEPR4均衡。 EEPR4序列检测器根据与预定网格码约束匹配的时变状态机进行操作。 因为状态机是时变的，所以在现有技术中数据流必须在序列检测器的输入端而不是在输出端被同步。 本发明提供一种容错同步标记检测器，其在输入到序列检测器之前，从EEPR4信道样本中检测同步标记。 在一个实施例中，同步标记检测器在读取信号采样值和目标同步标记的目标采样值之间累积平方误差; 当累积的平方误差小于预定的下限阈值时，检测同步标记。 在替代实施例中，同步标记检测器计算读取信号采样值和目标同步标记的目标采样值之间的相关性; 当相关性大于预定的上限阈值时，检测同步标记。 相关同步标记检测器是优选实施例，因为它对直流不敏感。 它在检测短同步标记方面具有出色的性能，并且可以实现为两个级联有限脉冲响应滤波器，而不需要乘法器或平方器。