-
1.发明授权Semiconductor device comprising transition detecting circuit and method of activating the same 有权包括转换检测电路的半导体器件及其激活方法公开(公告)号：US07127598B2
公开(公告)日：2006-10-24
申请号：US10322587
申请日：2002-12-19
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.
摘要翻译： 半导体器件包括内部电源，至少一个半导体电路块，延迟电路和检测电路。 初始化时，内部电源输出初始化完成信号。 半导体电路块基于由内部电源产生的电压进行工作。 延迟电路延迟初始化完成信号。 检测电路响应于由延迟电路延迟的初始化完成信号和外部输入的第一输入信号，命令半导体电路块开始操作。
-
2.发明授权Ferroelectric memory device having ferroelectric capacitor and method of reading out data therefrom 失效具有铁电电容器的铁电存储器件和从其读出数据的方法公开(公告)号：US07016216B2
公开(公告)日：2006-03-21
申请号：US10680394
申请日：2003-10-08
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes memory cells, a memory cell block, a sense amplifier, a precharge circuit, a bit line drive circuit, and a plate line drive circuit. Each of the memory cells has a cell transistor and a ferroelectric capacitor in between a source and drain of the cell transistor. The memory cell block includes the memory cells that are series connected between a bit line via a block select transistor and a plate line. The sense amplifier amplifies data read out from the memory cell, and generates one of a first potential and a second potential higher than the first potential in accordance with the read-out data. The precharge circuit precharges the bit line at a third potential that is higher than the first potential and lower than the second potential. The bit line drive circuit sets the bit line at a fourth potential.
摘要翻译： 铁电存储器件包括存储单元，存储单元块，读出放大器，预充电电路，位线驱动电路和板线驱动电路。 每个存储单元在单元晶体管的源极和漏极之间具有单元晶体管和铁电电容器。 存储单元块包括串联连接在经由块选择晶体管的位线和板线之间的存储单元。 读出放大器放大从存储单元读出的数据，根据读出的数据产生高于第一电位的第一电位和第二电位中的一个。 预充电电路在比第一电位高且低于第二电位的第三电位预充电位线。 位线驱动电路将位线设置为第四个电位。
-
公开(公告)号：US06765831B2
公开(公告)日：2004-07-20
申请号：US10428763
申请日：2003-05-05
IPC分类号： G11C800
CPC分类号： G11C11/22
摘要： A semiconductor integrated circuit device includes a memory array, address buffer, address decoder, and controller. The memory array includes a memory cell array in which destructive read-out memory cells are integrated. The address buffer outputs an internal address signal corresponding to an input external address signal. The address decoder decodes the internal address signal and outputs a memory cell selection signal on the basis of the decode result. The controller parallel-executes wait processing of keeping the address buffer in a wait state until the lapse of a skew time after transition of the external address signal is detected, and decode processing until the memory cell selection signal changes from an invalid state to a valid state in response to output of the internal address signal.
-
公开(公告)号：US06744302B2
公开(公告)日：2004-06-01
申请号：US10310053
申请日：2002-12-05
IPC分类号： G05F110
CPC分类号： G05F3/24
摘要： A voltage generator circuit generates a voltage supplied to an internal circuit. The voltage generator circuit includes first, second, and third switching elements each having first and second terminals. The first terminal of each of the switching elements is connected to the power source terminal supplied with a power source voltage. First, second, and third transistors each have a current path which has first and second ends. The first ends of the first, second, and third transistors are respectively connected to the second terminals of the first, second, and third switching elements. The first, second, and third transistors have respectively first, second, and third driving capabilities. The first, second, and third driving capabilities are different from each other. The second ends of the current paths of the first, second, and third transistors are connected to an output terminal which outputs the voltage supplied to the internal circuit.
摘要翻译： 电压发生器电路产生提供给内部电路的电压。 电压发生器电路包括具有第一和第二端子的第一，第二和第三开关元件。 每个开关元件的第一端子连接到被提供有电源电压的电源端子。 第一，第二和第三晶体管各自具有第一和第二端的电流路径。 第一，第二和第三晶体管的第一端分别连接到第一，第二和第三开关元件的第二端子。 第一，第二和第三晶体管分别具有第一，第二和第三驱动能力。 第一，第二和第三驾驶能力彼此不同。 第一，第二和第三晶体管的电流路径的第二端连接到输出提供给内部电路的电压的输出端子。
-
5.发明授权Power supply circuit that outputs a voltage stepped down from a power supply voltage 失效输出从电源电压降压的电源的电源电路公开(公告)号：US08134349B2
公开(公告)日：2012-03-13
申请号：US12404438
申请日：2009-03-16
IPC分类号： G05F1/613
CPC分类号： G05F1/56
摘要： A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.
摘要翻译： 电源电路具有恒压电路，第一MOS晶体管，第二MOS晶体管，第三MOS晶体管，第一分压电路，输出通过将输出端子的电压除以第一分压而得到的第一分压 以及馈送有参考电压的第一差分放大器电路和第一分压，并且具有连接到第二MOS晶体管的栅极的输出。 当第一分压高于参考电压时，第一差分放大器电路输出信号以接通第二MOS晶体管，并且当第一分压电压较低时，第一差分放大器电路输出关闭第二MOS晶体管的信号 比参考电压。
-
公开(公告)号：US07269049B2
公开(公告)日：2007-09-11
申请号：US11046878
申请日：2005-02-01
IPC分类号： G11C11/22
摘要： A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.
摘要翻译： 排列多个铁电存储单元。 排列在同一列中的每个存储单元的一个端子共同连接到第一位线。 排列在同一行中的存储单元的晶体管的栅极共同连接到字线。 排列在同一列或同一行中的每个存储单元的另一个端子共同连接到单元格板线。 第二位线与参考电压供应电路连接。 第一和第二位线与数据读取电路连接。 数据读取电路包括读出放大器和电流镜像电路，其具有连接到第一和第二位线的一对电流输入节点，并且将流过第一和第二位线之一的相同电流传送到另一位线。
-
公开(公告)号：US20060279977A1
公开(公告)日：2006-12-14
申请号：US11447940
申请日：2006-06-07
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a voltage to the other electrode of the ferroelectric capacitor. In a read operation of data, a first voltage is applied to the plate line. In a write operation of data, a second voltage different from the first voltage is applied to the plate line, and a voltage which is higher or lower than the second voltage is applied to the bit line.
摘要翻译： 铁电存储器件包括电池块，位线和板线。 电池块包括铁电电容器和晶体管开关。 位线向铁电电容器的一个电极施加电压。 板线向铁电电容器的另一个电极施加电压。 在数据的读取操作中，向板线施加第一电压。 在数据的写入操作中，不同于第一电压的第二电压被施加到板线，并且高于或低于第二电压的电压被施加到位线。
-
8.发明申请公开(公告)号：US20070058414A1
公开(公告)日：2007-03-15
申请号：US11392614
申请日：2006-03-30
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G06F11/1044
摘要： A semiconductor memory device includes a memory cell including a ferroelectric capacitor and a cell transistor and storing binary data at a first potential level and a second potential level which is higher than the first potential level, a bit line which reads the binary data from the memory cell, a correction circuit which corrects an error of the binary data read from the memory cell via the bit line, and a setting circuit which sets to the first potential a potential of the bit line connected to the memory cell from which at least the binary data is read, after the binary data is transferred to the correction circuit. The device further includes a control circuit which controls the potential of the bit line connected to the memory cell from which the binary data is read, in accordance with a result of error correction of the binary data.
摘要翻译： 半导体存储器件包括：存储单元，其包括铁电电容器和单元晶体管，并存储第二电位电平和第二电位高于第一电位电平的二进制数据;从存储器读出二进制数据的位线 单元，校正经由位线从存储单元读取的二进制数据的误差的校正电路，以及设置电路，其将连接到存储单元的位线的电位设置为第一电位，至少二进制 在将二进制数据传送到校正电路之后，读取数据。 该装置还包括控制电路，该控制电路根据二进制数据的纠错结果来控制连接到从其读取二进制数据的存储单元的位线的电位。
-
公开(公告)号：US20060023484A1
公开(公告)日：2006-02-02
申请号：US11046878
申请日：2005-02-01
IPC分类号： G11C11/22
摘要： A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.
摘要翻译： 排列多个铁电存储单元。 排列在同一列中的每个存储单元的一个端子共同连接到第一位线。 排列在同一行中的存储单元的晶体管的栅极共同连接到字线。 排列在同一列或同一行中的每个存储单元的另一个端子共同连接到单元格板线。 第二位线与参考电压供应电路连接。 第一和第二位线与数据读取电路连接。 数据读取电路包括读出放大器和电流镜像电路，其具有连接到第一和第二位线的一对电流输入节点，并且将流过第一和第二位线之一的相同电流传送到另一位线。
-
10.发明授权Semiconductor memory device having folded bit line array and an open bit line array with imbalance correction 失效具有折叠位线阵列的半导体存储器件和具有不平衡校正的开放位线阵列
公开(公告)号：US5761109A
公开(公告)日：1998-06-02
申请号：US614537
申请日：1996-03-13
IPC分类号： G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C11/4097
摘要： A dynamic semiconductor memory device according to the present invention comprises at least first and second memory cell arrays having a plurality of memory cells selectively arranged at respective intersections of a plurality of word lines and a plurality of bit lines, a first sense amplifier section connected at an end of the first cell array to a plurality of bit line pairs formed by part of the plurality of bit lines of the first cell array, the plurality of bit line pairs having a folded bit line configuration, a second sense amplifier section connected to sets of bit line pairs, each formed by one of the remaining bit lines of the first cell array and one of part of the plurality of bit lines of the second cell array, the plurality of bit line pairs having an open bit line configuration, and a correction circuit for correcting the level of ease for reading data "0" and that of reading data "1".
摘要翻译： 根据本发明的动态半导体存储器件包括至少第一和第二存储器单元阵列，其具有选择性地布置在多个字线和多个位线的各个交点处的多个存储器单元，第一读出放大器部分连接在 第一单元阵列的一端到由第一单元阵列的多个位线的一部分形成的多个位线对，多个位线对具有折叠位线配置，第二读出放大器部分连接到组 的位线对，每个位线对由第一单元阵列的剩余位线之一和第二单元阵列的多个位线的一部分之一形成，多个位线对具有打开的位线配置，以及 用于校正读取数据“0”的容易程度的校正电路和读取数据“1”的校正电路。
-
-
-
-
-
-
-
-
-
搜索结果
263 条记录 (耗时 0.035 秒)
