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1.发明授权公开(公告)号：US06188767B1
公开(公告)日：2001-02-13
申请号：US09069586
申请日：1998-04-29
IPC分类号： H04L932
CPC分类号： H04W4/06 , H04B7/2628
摘要： The present invention encompasses a base station and method of providing communication services to a plurality of communication units. The method includes the steps of sending communication information between the base station and at least two of the plurality of communication units. A first step of identifying communication units produces a group identifier. A scrambling code, based at least in part on the group identifier, is then used to encode the communication information for transmission.
摘要翻译： 本发明包括向多个通信单元提供通信服务的基站和方法。 该方法包括在基站与多个通信单元中的至少两个之间发送通信信息的步骤。 识别通信单元的第一步产生组标识符。 至少部分地基于组标识符的扰码被用于对通信信息进行编码以进行传输。
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2.发明授权
公开(公告)号：US5093632A
公开(公告)日：1992-03-03
申请号：US576333
申请日：1990-08-31
CPC分类号： H03L7/1976
摘要： A latched accumulator fractional-N synthesizer having reduced residual error for use in digital radio transcievers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615,617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).
摘要翻译： 公开了一种用于数字无线电转接器的具有减小的残余误差的锁存的累加器分数N合成器。 合成器的分频器（103）的除数随时间通过累加器进位输出数字序列的总和而变化，这导致频率增量等于参考频率的一部分。 累加器（615,617）被锁存，使得在发生时钟脉冲时，数据通过每个累加器一次一个时钟脉冲步进传送，使得通过系统的延迟等于仅一个累加器的延迟。 从最高阶累加器（621）的锁存输出中减去第二高阶累加器（619）的锁存输出，并在施加到环路滤波器（109）之前进行微分。
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公开(公告)号：US4879533A
公开(公告)日：1989-11-07
申请号：US176541
申请日：1988-04-01
CPC分类号： H01P1/2056 , H01P1/2136
摘要： A surface mount dielectric block filter with an integral transmission line connection to external circuitry is disclosed. In order to connect an input/output capacitor metallized on the surface of the dielectric block to a substrate upon which the dielectric block is directly mounted, a transmission line of appropriate characteristic impedance disposed on the surface of the dielectric block is connected between one plate of the metallized capacitor and an input/output terminal. Two such dielectric block filters may be coupled together to form a radio transceiver duplexer.
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4.发明授权
公开(公告)号：US4829543A
公开(公告)日：1989-05-09
申请号：US128976
申请日：1987-12-04
申请人： David E. Borth , Chih-Fei Wang , Duane C. Rabe , Gerald P. Labedz
发明人： David E. Borth , Chih-Fei Wang , Duane C. Rabe , Gerald P. Labedz
CPC分类号： H04W56/0085 , H04L7/042
摘要： A method and apparatus for phase-coherently demodulating a multipath-impaired time division multiple access QPSK data timeslot is disclosed. A quadrature separator generates multipath-impaired intermediate signals which, during a predetermined synchronizing sequence for the timeslot, are applied to a pair of synchronizing correlators to generate quadrature multipath profiles. These profiles then are used to modify subsequently received QPSK timeslot signals at the separator outputs to coherently construct multipath compensated I and Q channel data.
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公开(公告)号：US07512795B2
公开(公告)日：2009-03-31
申请号：US11028872
申请日：2005-01-04
申请人： Ronald F. Buskey , Larry C. Puhl , Duane C. Rabe
发明人： Ronald F. Buskey , Larry C. Puhl , Duane C. Rabe
IPC分类号： G06F21/00
CPC分类号： H04L9/3271 , H04M1/72522
摘要： A method and apparatus authenticates a component (450) for use in a device (100). The device memory (122) stores a predetermined challenge and a predetermined response (212) associated with the predetermined challenge. The method detects whether the component has been coupled to the device. If the component has been detected (206), the predetermined challenge is provided to the component (208). If a component response is received within a predetermined response time (210), it is compared to the predetermined response. The component is disabled (214) if either the component response is not received within the predetermined response time or the component response is received within the predetermined response time but the component response is not equivalent to the predetermined response. The component is enabled (216) if the component response is received within the predetermined response time and the component response is equivalent to the predetermined response.
摘要翻译： 一种方法和设备认证用于设备（100）中的组件（450）。 设备存储器（122）存储与预定挑战相关联的预定挑战和预定响应（212）。 该方法检测组件是否已耦合到设备。 如果已经检测到组件（206），则向组件（208）提供预定挑战。 如果在预定响应时间（210）内接收到分量响应，则将其与预定响应进行比较。 如果在预定响应时间内没有接收到分量响应或者在预定响应时间内接收到分量响应，但是分量响应不等于预定响应，则分量被禁用（214）。 如果在预定的响应时间内接收到分量响应并且分量响应等于预定响应，则分量被启用（216）。
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6.发明授权Method and apparatus for operating with a hopping control channel in a communication system 失效用于在通信系统中与跳频控制信道一起操作的方法和装置
公开(公告)号：US5506863A
公开(公告)日：1996-04-09
申请号：US112820
申请日：1993-08-25
申请人： Reuven Meidan , Duane C. Rabe , Michael D. Kotzin
发明人： Reuven Meidan , Duane C. Rabe , Michael D. Kotzin
IPC分类号： H04L27/10 , F02B3/06 , F02F1/16 , F02F11/00 , H04B1/713 , H04B1/7156 , H04B7/208 , H04B7/26 , H04L27/18 , H04W48/12
CPC分类号： F02F1/166 , F02F11/002 , H04B1/713 , H04B7/208 , H04W48/12 , F02B3/06 , F02F2007/0063 , H04B2001/71563
摘要： A communication unit for use in a communication system is provided which includes a hopping mechanism which hops communication frames over a plurality of carrier frequencies according to a predetermined hopping pattern. At least one of the communication frames preferably includes a synchronization channel time slot having data bits from which the predetermined hopping pattern may be derived. In addition, a communication unit is provided which includes a signal acquisition mechanism for initially acquiring a predetermined hopping pattern that specifies the sequence over which hop frames are hopped over a plurality of carrier frequencies. Also, this communication unit includes a hopping mechanism for hopping receiving frequency according to the predetermined hopping pattern such that a control channel may be detected. In an alternative embodiment, either communication unit may derive the predetermined hopping pattern from detected global position satellite information.
摘要翻译： 提供一种在通信系统中使用的通信单元，其包括跳频机制，该跳频机制根据预定的跳频模式跳越多个载波频率上的通信帧。 通信帧中的至少一个优选地包括具有数据比特的同步信道时隙，可以从其导出预定的跳频模式。 此外，提供一种通信单元，其包括用于最初获取预定跳频图案的信号获取机构，该预定跳频图案指定在多个载波频率上跳过跳帧的序列。 此外，该通信单元包括跳频机构，用于根据预定的跳频模式跳频接收频率，从而可以检测控制信道。 在替代实施例中，通信单元可以从检测到的全球定位卫星信息导出预定的跳频模式。
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公开(公告)号：US5055802A
公开(公告)日：1991-10-08
申请号：US516993
申请日：1990-04-30
CPC分类号： H03C3/0933 , H03C3/0925 , H03L7/1976
摘要： A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.
摘要翻译： 公开了采用至少二阶Σ-Δ调制器的分数N合成器。 来自Σ-Δ调制器的输出累加器的最高有效位用作循环分频器的可变因数的进位控制。 引入到合成器的调制作为Σ-Δ调制器的数字数字输入的一部分，并且通过选择大数作为循环除数除数的分数部分的分母来减少寄生信号输出。
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公开(公告)号：US5966667A
公开(公告)日：1999-10-12
申请号：US891758
申请日：1997-07-14
摘要： A dual mode communication device (102) includes a first radio (124) operable according to a first mode and a second radio (126) operable according to a second mode. A common user interface (130) controls both the first radio and the second radio. Using two, complete, preexisting radios reduces development and manufacturing costs of the dual mode communication device.
摘要翻译： 双模式通信设备（102）包括可根据第一模式操作的第一无线电（124）和可根据第二模式操作的第二无线电（126）。 公共用户界面（130）控制第一无线电和第二无线电。 使用两个完整的预先存在的无线电降低了双模式通信设备的开发和制造成本。
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公开(公告)号：US5192924A
公开(公告)日：1993-03-09
申请号：US786225
申请日：1991-10-31
CPC分类号： H03H7/0123 , H03H7/0115
摘要： A low pass filter circuit for a radiotelephone which filters harmonic, spectral components of a modulated signal generated by the radiotelephone. The filter circuit is comprised of inductors and capacitors wherein each inductor and each capacitor of the filter is comprised of a distributed-element portion and a discrete-element portion. The distributed element portions of each inductor and each capacitor of the filter attenuate higher-frequency, spectral components of a signal applied thereto. The discrete element components of each inductor and each capacitor of the filter attenuate lower-frequency, spectral components of the signal applied thereto.
摘要翻译： 一种用于无线电话机的低通滤波器电路，其对由无线电话机产生的调制信号的谐波，频谱分量进行滤波。 滤波器电路由电感器和电容器组成，其中滤波器的每个电感器和每个电容器由分布元件部分和离散元件部分组成。 每个电感器的分布元件部分和滤波器的每个电容器衰减施加到其上的信号的较高频率的频谱分量。 每个电感器和滤波器的每个电容器的分立元件分量衰减施加到其上的信号的较低频率的频谱分量。
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公开(公告)号：US5070310A
公开(公告)日：1991-12-03
申请号：US576342
申请日：1990-08-31
CPC分类号： H03L7/1976
摘要： A multiple latched accumulator fractional-N synthesizer for use in digital radio transceivers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The carry outputs of each accumulator are coupled through delays (645, 647, 649, 631, 633) equal to one less delay than the number of accumulators and added (635) such that all higher order accumulator carry outputs add to a net summation of zero so as to not upset the desired fractional setting of the first accumulator.
摘要翻译： 公开了一种用于数字无线电收发器的多锁存储器分数N合成器。 合成器的分频器（103）的除数随时间通过累加器进位输出数字序列的总和而变化，这导致频率增量等于参考频率的一部分。 累加器（615,617）被锁存，使得在发生时钟脉冲时，数据通过每个累加器一次一个时钟脉冲步进传送，使得通过系统的延迟等于仅一个累加器的延迟。 每个累加器的进位输出通过等于比累加器的数量少一个延迟（635）的延迟（645,647,649,631,633）耦合，使得所有高阶累加器运算输出增加到 零，以便不破坏第一累加器的期望的分数设置。
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