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17 条记录 (耗时 0.033 秒)

    Stable process induced correction bias circuitry for receivers on single-ended applications
    5.
    发明申请
    Stable process induced correction bias circuitry for receivers on single-ended applications 失效
    用于单端应用的接收器的稳定过程感应校正偏置电路

    公开(公告)号：US20060025089A1

    公开(公告)日：2006-02-02

    申请号：US10902559

    申请日：2004-07-29

    申请人： Manuel Salcido ,  Gilbert Yoh ,  Guy Humphrey ,  Salvador Salcido

    发明人： Manuel Salcido ,  Gilbert Yoh ,  Guy Humphrey ,  Salvador Salcido

    IPC分类号： H04Q7/20

    CPC分类号： H04L25/0276 ,  H04L25/0296

    摘要： A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.

    摘要翻译： 第二单端接收机，具有用于接收输入信号并输出​​一对相应输出信号的第一级，以及用于接收一对输出信号并输出​​相应的单输出信号的第二级。 第一和第二下拉晶体管耦合到第一和第二输入到第一级。 偏置电路电偏置第一级，第二级以及第一和第二下拉式晶体管，并且电源为这些部件提供电力。

    Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers
    8.
    发明申请
    Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers 有权
    用于控制电压集成电路输出驱动器的混合二进制/温度计代码

    公开(公告)号：US20050242830A1

    公开(公告)日：2005-11-03

    申请号：US10835906

    申请日：2004-04-30

    申请人： Guy Humphrey ,  David Linam

    发明人： Guy Humphrey ,  David Linam

    IPC分类号： H03K19/00 ,  H03K19/003

    CPC分类号： H03K19/0005

    摘要： A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

    摘要翻译： 采用混合二进制/温度计代码来调整具有阻抗网络的可变阻抗输出驱动器电路的输出阻抗，该阻抗网络包括多个阻抗支路，每个阻抗支路可根据混合二进制/温度计代码在电压源和 信号垫。 多个阻抗腿分成一组或多组二进制步进阻抗腿和对应的温度计步进阻抗腿。 混合二进制/温度计代码中的一组二进制校准信号根据二进制码和二进制/温度计代码中的温度计校准信号组合，给出一组给定的二进制步进阻抗支路，步进相应的温度计步进阻抗腿组 根据温度计代码，每次完全计数二进制集合的校准信号。

    CMOS buffer with hysteresis
    10.
    发明申请
    CMOS buffer with hysteresis 审中-公开
    具有迟滞的CMOS缓冲器

    公开(公告)号：US20050218933A1

    公开(公告)日：2005-10-06

    申请号：US10817668

    申请日：2004-04-02

    申请人： David Linam ,  Guy Humphrey

    发明人： David Linam ,  Guy Humphrey

    IPC分类号： H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A CMOS buffer with hysteresis is implemented. In one embodiment, an upper-trip circuit (102) and a lower-trip circuit (104) are implemented with CMOS inverters. The upper-trip circuit (102) and the lower-trip circuit (104) provides output to a pull-up device (110) and a pull-down device (111), respectively. The pull-up device (110) and the pull-down device (111) both generate an output signal onto a net (112). A bus holder (114) is coupled to the net (112) and maintains the output signal. In addition, an output circuit (116) is coupled to the net (112) and processes the output signal. In one embodiment, the output circuit is implemented with a CMOS buffer and functions as a buffer with hysteresis. In another embodiment, the output circuit is implemented with an inverter and functions as an inverting buffer with hysteresis. In a third embodiment, the output circuit is implemented with a connection (i.e., signal conveyance) and functions as a non-inverting buffer with hysteresis.

    摘要翻译： 实现了具有迟滞的CMOS缓冲器。 在一个实施例中，上行跳闸电路（102）和下跳闸电路（104）由CMOS反相器实现。 上跳闸电路（102）和下跳闸电路（104）分别向上拉装置（110）和下拉装置（111）提供输出。 上拉装置（110）和下拉装置（111）都在网（112）上产生输出信号。 总线保持器（114）耦合到网（112）并维持输出信号。 此外，输出电路（116）耦合到网（112）并处理输出信号。 在一个实施例中，输出电路用CMOS缓冲器实现，并且用作具有滞后的缓冲器。 在另一个实施例中，输出电路用逆变器实现，并且用作具有迟滞的反相缓冲器。 在第三实施例中，输出电路用连接（即信号传送）实现，并且用作具有迟滞的非反相缓冲器。