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23 条记录 (耗时 0.027 秒)

    Method and composition of preparing polymeric fracturing fluids
    1.
    发明申请
    Method and composition of preparing polymeric fracturing fluids 有权
    制备聚合物压裂液的方法和组成

    公开(公告)号：US20070114035A1

    公开(公告)日：2007-05-24

    申请号：US11285440

    申请日：2005-11-22

    申请人： Michael Parris ,  Ismail El Kholy

    发明人： Michael Parris ,  Ismail El Kholy

    IPC分类号： E21B43/267 ,  E21B43/26

    CPC分类号： C09K8/68 ,  C09K8/685 ,  C09K8/88 ,  C09K8/887

    摘要： In the presence of certain polyols, a guar gum or similar polysaccharide thickener solution is boron crosslinked before achievement of complete hydration of the thickener, without compromising the viscosity level achieved in a fracturing fluid by the time it is pumped into the wellbore and fractures the subterranean formation adjacent the wellbore. Methods continuously involve hydrating a polysaccharide thickener to an extent of 10% to 75%, but less than full hydration. Before 75% hydration is exceeded, a boron crosslinker is added. Upon addition of the boron crosslinker, the fluid is injected into the wellbore to stimulate hydrocarbon production. Because less time is needed for hydration, well site mixing equipment is down-sized smaller to achieve better efficiency and cost savings.

    摘要翻译： 在存在某些多元醇的情况下，瓜尔胶或类似的多糖增稠剂溶液在实现增稠剂的完全水合之前是交联的硼，而不损害在压裂液被泵入井筒中时达到的粘度水平，并破裂了地下 形成在井眼附近。 方法连续地将多糖增稠剂水合至10％至75％，但不足于完全水合。 在超过75％水合之前，加入硼交联剂。 加入硼交联剂后，将流体注入井眼以刺激烃的生产。 由于水合时间较短，井场混合设备规模较小，可实现更好的效率和成本节约。

    Concentrated suspensions
    2.
    发明授权
    Concentrated suspensions 有权
    浓缩悬浮液

    公开(公告)号：US07199084B2

    公开(公告)日：2007-04-03

    申请号：US10103221

    申请日：2002-03-21

    申请人： Michael Parris ,  Geoff Robinson

    发明人： Michael Parris ,  Geoff Robinson

    IPC分类号： C09K8/18 ,  C09K8/20

    CPC分类号： C09K8/82 ,  C09K8/58 ,  C09K8/62 ,  C09K8/64

    摘要： Suspensions are provided of water-soluble materials in non-aqueous carrier fluids using suspension agents that include thixotropic agents and, optionally, organophilic clays. Methods of forming such suspensions are provided. Methods are also provided for using such suspensions to prepare aqueous solutions, in particular thickened aqueous solutions, in particular for use in oilfield treatments.

    摘要翻译： 使用包括触变剂和任选的亲有机粘土的悬浮剂在非水载体流体中提供水溶性材料的悬浮液。 提供了形成这种悬浮液的方法。 还提供了使用这种悬浮液来制备水溶液，特别是增稠的水溶液，特别是用于油田处理的方法。

    Powergating method and apparatus
    5.
    发明申请
    Powergating method and apparatus 有权
    电源起动方法和装置

    公开(公告)号：US20060022742A1

    公开(公告)日：2006-02-02

    申请号：US10900505

    申请日：2004-07-28

    申请人： Michael Parris ,  Kim Hardee

    发明人： Michael Parris ,  Kim Hardee

    IPC分类号： H03K17/687

    CPC分类号： H03K19/0016

    摘要： A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.

    摘要翻译： 电源门控电路包括具有耦合到VCC的源极的P沟道晶体管，用于接收第一升压或非升压功率门控控制信号的栅极和形成内部开关VCC电源的漏极。 N沟道晶体管具有耦合到VSS的源极，用于接收第二升压或非升压的功率门控控制信号的栅极以及形成内部开关VSS电源的漏极。 电源门电路还包括用于在待机模式期间将第一和第二内部电源电压强制为中点参考电压的电路。

    Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices
    8.
    发明申请
    Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices 审中-公开
    用于缓存集成电路存储器件的低功耗数据保留待机模式技术中的缓存和标签掉电功能

    公开(公告)号：US20060005053A1

    公开(公告)日：2006-01-05

    申请号：US10881767

    申请日：2004-06-30

    申请人： Oscar Jones ,  Douglas Butler ,  Michael Parris

    发明人： Oscar Jones ,  Douglas Butler ,  Michael Parris

    IPC分类号： G06F1/26

    CPC分类号： G06F12/0804 ,  G06F1/3203 ,  G06F1/3275 ,  G06F2212/1028 ,  G06F2212/3042 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： A cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices, in particular cached dynamic random access memory (DRAM) and cached static random access memory (SRAM), wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby. When power-down standby is exited, the cache operations are enabled as soon as the cache, tag and control circuitry are powered-up and a clear tag sequence is executed.

    摘要翻译： 用于缓存的集成电路存储器件（特别是缓存的动态随机存取存储器（DRAM））和高速缓存的静态随机存取存储器（SRAM）的低功率数据保持待机模式技术中的高速缓存和标签掉电功能，其中高速缓存中的数据 在输入掉电时，从高速缓存写入主存储器阵列（回写操作），使得高速缓存，标签和大部分高速缓存控制逻辑在掉电待机模式下可以掉电。 如果使用DRAM高速缓存，则可以禁止刷新周期到DRAM高速缓存，因为它已经掉电，从而在自刷新掉电待机期间可以实现额外的功率节省。 当退出备用电源时，一旦高速缓存，标签和控制电路通电并且执行了清晰的标签序列，就启用高速缓存操作。

    Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array
    9.
    发明授权
    Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array 失效
    用于同时寻址多行存储器阵列多列的存储器件电路和方法

    公开(公告)号：US5671392A

    公开(公告)日：1997-09-23

    申请号：US419909

    申请日：1995-04-11

    申请人： Michael Parris ,  H. Kent Stalnaker

    发明人： Michael Parris ,  H. Kent Stalnaker

    IPC分类号： G11C11/407 ,  G11C8/12 ,  G11C11/401 ,  G11C29/28 ,  G11C29/34 ,  G06F12/00

    CPC分类号： G11C8/12 ,  G11C29/28

    摘要： A circuit and method for a memory device, such as a synchronous dynamic random access memory (SDRAM) having at least two memory banks. Columns of at least two memory banks are concurrently addressable to permit data to be written to, or read from, the at least two memory banks concurrently. By writing data concurrently to more than one memory bank, testing of the memory of the memory device can be effectuated in a reduced period of time. Data can also be written or read from a single bank in a multi-bank RAM without requiring that a particular bank be specified during a read/write command.

    摘要翻译： 一种用于存储器件的电路和方法，例如具有至少两个存储体的同步动态随机存取存储器（SDRAM）。 至少两个存储体的列同时可寻址以允许数据同时写入或读取至少两个存储体。 通过将数据同时写入多个存储体，可以在减少的时间段内对存储器件的存储器进行测试。 也可以在多存储体RAM中从单个存储体中写入或读取数据，而不需要在读取/写入命令期间指定特定的存储体。

    One transistor memory cell with programmable capacitance divider
    10.
    发明授权
    One transistor memory cell with programmable capacitance divider 失效
    一个具有可编程电容分压器的晶体管存储单元

    公开(公告)号：US4914627A

    公开(公告)日：1990-04-03

    申请号：US292776

    申请日：1989-01-03

    申请人： S. Sheffield Eaton, Jr. ,  Michael Parris

    发明人： S. Sheffield Eaton, Jr. ,  Michael Parris

    IPC分类号： G11C11/22 ,  G11C14/00

    CPC分类号： G11C14/0072 ,  G11C11/22 ,  G11C14/00

    摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

    摘要翻译： 偏振器用作可编程电容分压器。 两个铁电电容器串联耦合以形成公共节点和两个极端极。 两个电容器的极化通过将两极接地而设置，然后将它们两者都设置为VCC，同时在与要存储的数据相对应的公共节点处施加电压。 因此，当一个极点保持在VSS时，另一个极点从VSS脉冲到VCC，公共节点浮动。 在VSS和VCC之间的中点之上或之下的公共节点处产生电压，并且将指示存储的数据。 电容分压器根据数据进行编程。 一个这样的分频器被添加到DRAM存储器单元以形成阴影DRAM单元。 将两个这样的分频器添加到静态RAM存储器单元中以形成阴影静态RAM单元。 相同的分配器布置可在易失性和非易失性模式下操作。 通过使用PZT作为54:46摩尔比的电介质来改善。