公开(公告)号：US08065646B2

公开(公告)日：2011-11-22

申请号：US12066225

申请日：2005-09-07

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen ,  Eitan Zmora

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen ,  Eitan Zmora

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/505 ,  G06F17/5031

摘要： A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

摘要翻译： 一种用于分析集成电路的设计的方法，所述方法包括定义要提供给集成电路的信号的可能定时并计算保持违规; 其特征在于，响应于信号的可能定时，包括确定时钟事件与理想地在时钟事件之前的相应数据/控制事件之间的关系的阶段; 以及响应于所述关系确定保持参数。 一种在其上存储有一组指令的计算机可读介质，所述指令集在由处理器执行时使得所述处理器定义所设计的组件的至少一个内部延迟，其特征在于，使所述处理器定义被表征的单元 多个保持时间和多个设置值，用于某个时钟偏移值。

公开(公告)号：US20080250372A1

公开(公告)日：2008-10-09

申请号：US12066225

申请日：2005-09-07

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen ,  Eitan Zmora

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen ,  Eitan Zmora

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031

摘要： A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

摘要翻译： 一种用于分析集成电路的设计的方法，所述方法包括定义要提供给集成电路的信号的可能定时并计算保持违规; 其特征在于，响应于信号的可能定时，包括确定时钟事件与理想地在时钟事件之前的相应数据/控制事件之间的关系的阶段; 以及响应于所述关系确定保持参数。 一种在其上存储有一组指令的计算机可读介质，所述指令集在由处理器执行时使得所述处理器定义所设计的组件的至少一个内部延迟，其特征在于，使所述处理器定义被表征的单元 多个保持时间和多个设置值，用于某个时钟偏移值。

公开(公告)号：US08850232B2

公开(公告)日：2014-09-30

申请号：US12919541

申请日：2008-03-19

申请人： Michael Priel ,  Asaf Ashkenazi ,  Dan Kuzmin ,  Anton Rozen

发明人： Michael Priel ,  Asaf Ashkenazi ,  Dan Kuzmin ,  Anton Rozen

IPC分类号： G06F12/14 ,  G08B29/00 ,  G06F21/55 ,  G06F21/86

CPC分类号： G06F21/558 ,  G06F21/554 ,  G06F21/755 ,  G06F21/86

摘要： A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.

摘要翻译： 一种用于保护密码模块的设备和方法，该方法包括：当物理参数具有与加密模块正常工作的标称参数值不同的第一值时，估计适于故障的电路的功能。 当物理参数具有与标称参数值不同的第二值并且第一值和标称参数值之间的差小于第二值和标称参数值之间的差时，加密模块发生故障。 如果估计电路发生故障，则应用加密模块保护措施。

公开(公告)号：US07941716B2

公开(公告)日：2011-05-10

申请号：US11909394

申请日：2005-03-23

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G01R31/318541 ,  G01R31/318536 ,  H03K3/0375

摘要： A method for race prevention includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. A device having race prevention capabilities includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and a start point of a second scan mode activation period of the output latching logic.

摘要翻译： 一种防止竞赛的方法包括：选择性地向输入锁存逻辑提供数据或扫描数据，在第一扫描模式激活期间激活输入锁存逻辑，在第一扫描模式激活期和第二扫描模式激活之间引入实质的时间偏移 并且激活输出锁存逻辑，连接到输入锁存逻辑用于第二扫描模式激活周期。 具有防止竞争能力的装置包括：接口逻辑，输入锁存逻辑，输出锁存逻辑和控制逻辑。 接口逻辑适于选择性地向输入锁存逻辑提供数据或扫描数据。 控制逻辑适于在输入锁存逻辑的第一扫描模式激活周期的终点与输出锁存逻辑的第二扫描模式激活周期的起始点之间引入实质的时间差。

公开(公告)号：US09462556B2

公开(公告)日：2016-10-04

申请号：US13582769

申请日：2010-03-22

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC分类号： G06F9/00 ,  G06F1/32 ,  H04W52/02

CPC分类号： H04W52/0261 ,  G06F1/32 ,  G06F9/00 ,  Y02D70/00

摘要： An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.

摘要翻译： 集成电路装置包括信号处理系统，该信号处理系统具有通过第一生产过程制造的至少一个第一信号处理模块; 以及通过第二生产过程制造的至少一个第二信号处理模块，其中第二生产过程与第一生产过程不同。 信号处理系统还包括信号处理管理模块，其被布置成：确定集成电路装置的期望的系统性能; 确定信号处理系统的至少一个操作条件; 并且至少部分地基于：确定的期望系统性能来配置所述信号处理系统的信号处理操作模式; 所述至少一个确定的操作条件; 以及第一生产过程和第二生产过程中的至少一个。

公开(公告)号：US09429966B2

公开(公告)日：2016-08-30

申请号：US13979860

申请日：2011-01-31

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC分类号： G05F1/46 ,  G11C5/14

CPC分类号： G05F1/462 ,  G11C5/147 ,  G11C7/04 ,  G11C16/30

摘要： An integrated circuit (IC) device is provided that includes at least one internal voltage regulator arranged to receive a voltage supply signal at a first input thereof, receive a control signal at a second input thereof, regulate the received voltage supply signal in accordance with the received control signal, and provide a regulated voltage supply signal at an output thereof. The IC device further includes at least one voltage regulation power control module operably coupled to the second input of the at least one internal voltage regulator and arranged to provide the control signal thereto. The voltage regulation power control module is further arranged to receive at least one IC device conditional indication, and generate the control signal for the at least one internal voltage regulator based at least partly on an available thermal power budget for the IC device corresponding to the at least one IC device conditional indication.

摘要翻译： 提供一种集成电路（IC）装置，其包括至少一个内部电压调节器，其布置成在其第一输入处接收电压供应信号，在其第二输入处接收控制信号，根据 接收到的控制信号，并在其输出端提供稳压电压信号。 IC器件还包括至少一个电压调节功率控制模块，其可操作地耦合到所述至少一个内部电压调节器的第二输入端并被布置成向其提供控制信号。 电压调节功率控制模块还被布置成接收至少一个IC器件条件指示，并且至少部分地基于对应于所述at的IC器件的可用热功率预算来生成用于所述至少一个内部稳压器的控制信号 至少一个IC器件条件指示。

公开(公告)号：US09094001B2

公开(公告)日：2015-07-28

申请号：US13503862

申请日：2009-11-12

申请人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

发明人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

IPC分类号： G06F1/00 ,  H03K19/003 ,  G06F1/30 ,  G06F1/26 ,  G06F1/28

CPC分类号： H03K19/00346 ,  G06F1/26 ,  G06F1/28 ,  G06F1/305

摘要： An integrated circuit and a method. The integrated circuit includes an internal component having an output for providing a driven input signal; an output driver, connected to the internal component, for converting said driven input signal in an output signal; an output pad for outputting said output signal to a component outside the integrated circuit; a power grid configured to supply a supply voltage to the output driver; a controllable current consuming component connected to the power grid, said connectable current consuming component being controllable to consume current in accordance with a supply voltage change reduction pattern; a change detector connected to the internal component and the controllable current consuming component, for detecting a change in said driven input signal prior to said change resulting in a change in said output signal and to control said current consuming component to consume current in response to said detecting.

摘要翻译： 一种集成电路和方法。 集成电路包括具有用于提供驱动输入信号的输出的内部部件; 连接到内部组件的输出驱动器，用于在输出信号中转换所述驱动输入信号; 输出焊盘，用于将所述输出信号输出到集成电路外的部件; 配置为向输出驱动器提供电源电压的电网; 连接到电网的可控电流消耗部件，所述可连接电流消耗部件可控制以根据电源电压变化减小模式消耗电流; 连接到内部组件和可控电流消耗部件的变化检测器，用于在所述变化之前检测所述驱动输入信号的变化，导致所述输出信号的变化，并且响应于所述输入信号控制所述电流消耗部件消耗电流 检测。

公开(公告)号：US08381009B2

公开(公告)日：2013-02-19

申请号：US12376074

申请日：2006-08-03

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC分类号： G06F1/12

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.

摘要翻译： 一种具有电源管理功能的设备和用于电源管理的方法，所述方法包括：向设备的至少一个组件提供时钟信号和电源电压; 检测定时误差; 延迟一个时钟周期的一小部分并且响应于检测到的定时误差，提供给至少一个组件的时钟信号; 以及响应于至少一个检测到的定时误差来确定时钟信号频率和电源电压的电平。

公开(公告)号：US20120235732A1

公开(公告)日：2012-09-20

申请号：US13511321

申请日：2009-11-30

申请人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

发明人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

IPC分类号： G05F3/02

CPC分类号： H04L25/0272

摘要： An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled.

摘要翻译： 集成电路包括用于提供在电信号的传输中使用的参考电压的参考电压产生电路。 参考电压产生电路包括经由多个电阻元件可操作地耦合到多个信号节点的参考电压节点，使得参考电压节点将其耦合到的信号节点的电压值的平均值作为参考电压 。

公开(公告)号：US08112645B2

公开(公告)日：2012-02-07

申请号：US12179844

申请日：2008-07-25

申请人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

发明人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203

摘要： A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state.

摘要翻译： 一种系统，包括：存储器单元，适于存储指示与可能的状态持续时间相关联的可能的低功率状态持续时间和概率的状态持续时间统计; 以及功率控制器，适于：接收使电路进入下一状态的请求，并且如果在所述功率控制器未接收到的请求的接收之后的延迟时段期间，则辅助使所述电路进入下一状态 使电路退出下一状态的请求; 其中所述延迟周期是响应于：（i）下一状态持续时间统计，（ii）从进入下一状态获得的功率节省; 和（iii）与进入下一状态并退出下一状态相关联的功率损失。