公开(公告)号：US08665125B2

公开(公告)日：2014-03-04

申请号：US13569310

申请日：2012-08-08

申请人： Michael Reinhold ,  Martin Allinger ,  Frank Ohnhaeuser

发明人： Michael Reinhold ,  Martin Allinger ,  Frank Ohnhaeuser

IPC分类号： H03M1/10

CPC分类号： H03M1/1061 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

摘要： The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor.

摘要翻译： 该装置包括逐次逼近寄存器，包括多个电容器的电容数模转换器，多个电容器与第一侧耦合到公共节点; 比较器，耦合到公共节点，并且适于通过将公共节点处的电压与另一个电压电平进行比较来产生比特决定;以及SAR控制级，用于提供表示转换结果的数字代码。 该器件被配置为在校准模式下操作，其中器件被配置为通过将第一电容器的一侧耦合到参考电压来对多个电容器的第一电容器进行参考电压的采样，以执行常规转换周期， 所述多个电容器中的至少那些电容器的重要性低于第一电容器，并且提供用于校准第一电容器的常规转换周期的转换结果。

公开(公告)号：US20130044015A1

公开(公告)日：2013-02-21

申请号：US13569310

申请日：2012-08-08

申请人： Michael Reinhold ,  Martin Allinger ,  Frank Ohnhaeuser

发明人： Michael Reinhold ,  Martin Allinger ,  Frank Ohnhaeuser

IPC分类号： H03M1/12

CPC分类号： H03M1/1061 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

摘要： The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor.

摘要翻译： 该装置包括逐次逼近寄存器，包括多个电容器的电容数模转换器，多个电容器与第一侧耦合到公共节点; 比较器，耦合到公共节点，并且适于通过将公共节点处的电压与另一个电压电平进行比较来产生比特决定;以及SAR控制级，用于提供表示转换结果的数字代码。 该器件被配置为在校准模式下操作，其中器件被配置为通过将第一电容器的一侧耦合到参考电压来对多个电容器的第一电容器进行参考电压的采样，以执行常规转换周期， 所述多个电容器中的至少那些电容器的重要性低于第一电容器，并且提供用于校准第一电容器的常规转换周期的转换结果。

公开(公告)号：US20100214140A1

公开(公告)日：2010-08-26

申请号：US12711060

申请日：2010-02-23

申请人： Michael Reinhold ,  Frank Ohnhaeuser ,  Mikael Badenius

发明人： Michael Reinhold ,  Frank Ohnhaeuser ,  Mikael Badenius

IPC分类号： H03M1/06 ,  H03M1/66 ,  H03M1/00

CPC分类号： H03M1/1047 ,  H03M1/462 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

摘要： Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

摘要翻译： 逐次逼近寄存器（SAR）模数转换器（ADC）通常采用容性数模转换器（CDAC）来执行数据转换。 在这些CDAC中，电容值的匹配是重要的，对于传统的高分辨率SAR ADC，复杂的修整或校准程序可能太昂贵。 然而，这里提供了一个SAR ADC，与传统的SAR ADC相比，可以进行纠错，从而降低整体成本。

公开(公告)号：US08049654B2

公开(公告)日：2011-11-01

申请号：US12711060

申请日：2010-02-23

申请人： Michael Reinhold ,  Frank Ohnhaeuser ,  Mikael Badenius

发明人： Michael Reinhold ,  Frank Ohnhaeuser ,  Mikael Badenius

IPC分类号： H03M1/12

CPC分类号： H03M1/1047 ,  H03M1/462 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

摘要： Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

摘要翻译： 逐次逼近寄存器（SAR）模数转换器（ADC）通常采用容性数模转换器（CDAC）来执行数据转换。 在这些CDAC中，电容值的匹配是重要的，对于传统的高分辨率SAR ADC，复杂的修整或校准程序可能太昂贵。 然而，这里提供了一个SAR ADC，与传统的SAR ADC相比，可以进行纠错，从而降低整体成本。

公开(公告)号：US20100207791A1

公开(公告)日：2010-08-19

申请号：US12692763

申请日：2010-01-25

申请人： Frank Ohnhaeuser ,  Michael Reinhold

发明人： Frank Ohnhaeuser ,  Michael Reinhold

IPC分类号： H03M1/66 ,  H03M1/06 ,  H03M1/00

CPC分类号： H03M1/0612 ,  H03M1/0682 ,  H03M1/462 ,  H03M1/468 ,  H03M1/661 ,  H03M1/76 ,  H03M1/804

摘要： An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator configured to provide an INL compensation signal for reducing INL of the analog-to-digital conversion in response to the digital code.

摘要翻译： 提供了使用逐次逼近的用于模数转换的装置。 存在用于提供表示转换结果的数字代码的逐次逼近寄存器或SAR控制器，以及被配置为提供INL补偿信号的集成非线性（INL）补偿器，用于响应于所述INL补偿信号来减少所述模数转换的INL 数字代码。

公开(公告)号：US07196643B2

公开(公告)日：2007-03-27

申请号：US11347703

申请日：2006-02-03

申请人： Frank Ohnhaeuser ,  Michael Reinhold ,  Mikael Badenius

发明人： Frank Ohnhaeuser ,  Michael Reinhold ,  Mikael Badenius

IPC分类号： H03M1/06

CPC分类号： H03M1/645

摘要： A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words. Finally, each channel has a second digital filter that averages the demodulated data-words and supplies digital output data-words on the channel output, the carrier signal being suppressed in the output data-words.

摘要翻译： 低成本但又提供高分辨率和高噪声抑制的解算器装置包括载波信号发生器和两个处理通道，每个处理通道具有连接到不同的定子线圈和通道输出的模拟输入。 每个处理通道包括具有输出的Σ-Δ调制器，该输出提供表示从相应的定子线圈接收的模拟输入信号的比特流。 每个通道还包括第一数字滤波器，其接收来自Σ-Δ调制器的比特流，并将比特流转换成中间数字数据字。 此外，每个通道具有数字同步解调器，其与提供解调数据字的载波信号同步地解调中间数字数据字。 最后，每个通道具有第二数字滤波器，对解调的数据字进行平均，并在通道输出上提供数字输出数据字，载波信号被抑制在输出数据字中。

公开(公告)号：US08624767B2

公开(公告)日：2014-01-07

申请号：US13603179

申请日：2012-09-04

申请人： Konstantin Schmid ,  Michael Reinhold ,  Frank Ohnhaeuser

发明人： Konstantin Schmid ,  Michael Reinhold ,  Frank Ohnhaeuser

IPC分类号： H03M3/00

CPC分类号： H03M3/338 ,  H03M3/34 ,  H03M3/43 ,  H03M3/47

摘要： The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.

摘要翻译： 调制器包括第一和第二积分级和比较器，第一积分级是完全差分的，其具有：放大器，输入采样电容器组和反馈电容器组，并且第一积分级被配置为在模拟输入电压 在时钟周期的第一部分期间的一组输入电容器和在时钟周期的第二部分期间的一组输入电容器，并且在时钟周期的第一部分期间在一组反馈电容器上对反馈参考电压进行采样， 在时钟周期的第二部分期间的一组反馈电容器，以及从周期到周期的多组反馈电容器中随机选择第一组反馈电容器和第二组反馈电容器。

公开(公告)号：US20060170579A1

公开(公告)日：2006-08-03

申请号：US11347703

申请日：2006-02-03

申请人： Frank Ohnhaeuser ,  Michael Reinhold ,  Mikael Badenius

发明人： Frank Ohnhaeuser ,  Michael Reinhold ,  Mikael Badenius

IPC分类号： H03M3/00

CPC分类号： H03M1/645

摘要： A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words. Finally, each channel has a second digital filter that averages the demodulated data-words and supplies digital output data-words on the channel output, the carrier signal being suppressed in the output data-words.

摘要翻译： 低成本但又提供高分辨率和高噪声抑制的解算器装置包括载波信号发生器和两个处理通道，每个处理通道具有连接到不同的定子线圈和通道输出的模拟输入。 每个处理通道包括具有输出的Σ-Δ调制器，该输出提供表示从相应的定子线圈接收的模拟输入信号的比特流。 每个通道还包括第一数字滤波器，其接收来自Σ-Δ调制器的比特流，并将比特流转换成中间数字数据字。 此外，每个通道具有数字同步解调器，其与提供解调数据字的载波信号同步地解调中间数字数据字。 最后，每个通道具有第二数字滤波器，对解调的数据字进行平均，并在通道输出上提供数字输出数据字，载波信号被抑制在输出数据字中。

公开(公告)号：US20130278454A1

公开(公告)日：2013-10-24

申请号：US13603179

申请日：2012-09-04

申请人： Konstantin Schmid ,  Michael Reinhold ,  Frank Ohnhaeuser

发明人： Konstantin Schmid ,  Michael Reinhold ,  Frank Ohnhaeuser

IPC分类号： H03M3/02

CPC分类号： H03M3/338 ,  H03M3/34 ,  H03M3/43 ,  H03M3/47

摘要： The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.

摘要翻译： 调制器包括第一和第二积分级和比较器，第一积分级是完全差分的，其具有：放大器，输入采样电容器组和反馈电容器组，并且第一积分级被配置为在模拟输入电压 在时钟周期的第一部分期间的一组输入电容器和在时钟周期的第二部分期间的一组输入电容器，并且在时钟周期的第一部分期间在一组反馈电容器上对反馈参考电压进行采样， 在时钟周期的第二部分期间的一组反馈电容器，以及从周期到周期的多组反馈电容器中随机选择第一组反馈电容器和第二组反馈电容器。

公开(公告)号：US07944379B2

公开(公告)日：2011-05-17

申请号：US12692763

申请日：2010-01-25

申请人： Frank Ohnhaeuser ,  Michael Reinhold

发明人： Frank Ohnhaeuser ,  Michael Reinhold

IPC分类号： H03M1/06

CPC分类号： H03M1/0612 ,  H03M1/0682 ,  H03M1/462 ,  H03M1/468 ,  H03M1/661 ,  H03M1/76 ,  H03M1/804

摘要： An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator configured to provide an INL compensation signal for reducing INL of the analog-to-digital conversion in response to the digital code.

摘要翻译： 提供了使用逐次逼近的用于模数转换的装置。 存在用于提供表示转换结果的数字代码的逐次逼近寄存器或SAR控制器，以及被配置为提供INL补偿信号的集成非线性（INL）补偿器，用于响应于所述INL补偿信号来减少所述模数转换的INL 数字代码。