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1.发明申请System and method for thermal monitoring of IC using sampling periods of invariant duration 失效使用不变持续时间的采样周期对IC进行热监测的系统和方法公开(公告)号：US20060173645A1
公开(公告)日：2006-08-03
申请号：US11050324
申请日：2005-02-03
IPC分类号： G01K1/00
CPC分类号： G01K7/425 , G01K7/32 , H01L23/34 , H01L2924/0002 , Y10S323/907 , H01L2924/00
摘要： A system and method are provided for monitoring temperature within a specified integrated circuit. Usefully, the system comprises at least one oscillator device proximate to the integrated circuit for generating signal pulses at a frequency that varies as a function of the temperature adjacent to the oscillator device. The system further comprises a control unit for establishing sample acquisition periods of invariant time duration based on an time invariant reference clock. A sampling component is coupled to count the number of pulses generated by the oscillator device during each of a succession of the time invariant sample acquisition periods, and a threshold component responsive to the respective count values for the succession of sample acquisition periods provides notice when at least some of the count values have a value associated with a prespecified excessive temperature level.
摘要翻译： 提供了一种用于监测指定集成电路内的温度的系统和方法。 有用地，系统包括靠近集成电路的至少一个振荡器装置，用于以与振荡器装置相邻的温度变化的频率产生信号脉冲。 该系统还包括控制单元，用于基于时不变参考时钟建立不变时间持续时间的采样周期。 一个采样分量被耦合以对在时间不变样本采集周期中的每一个期间由振荡器装置产生的脉冲数进行计数，并且对于连续的采样采集周期响应于各个计数值的阈值分量提供了当在 至少一些计数值具有与预先指定的过高温度水平相关联的值。
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2.发明授权System and method for thermal monitoring of IC using sampling periods of invariant duration 失效使用不变持续时间的采样周期对IC进行热监测的系统和方法公开(公告)号：US07197419B2
公开(公告)日：2007-03-27
申请号：US11050324
申请日：2005-02-03
IPC分类号： G06F17/40
CPC分类号： G01K7/425 , G01K7/32 , H01L23/34 , H01L2924/0002 , Y10S323/907 , H01L2924/00
摘要： A system and method are provided for monitoring temperature within a specified integrated circuit. Usefully, the system comprises at least one oscillator device proximate to the integrated circuit for generating signal pulses at a frequency that varies as a function of the temperature adjacent to the oscillator device. The system further comprises a control unit for establishing sample acquisition periods of invariant time duration based on an time invariant reference clock. A sampling component is coupled to count the number of pulses generated by the oscillator device during each of a succession of the time invariant sample acquisition periods, and a threshold component responsive to the respective count values for the succession of sample acquisition periods provides notice when at least some of the count values have a value associated with a prespecified excessive temperature level.
摘要翻译： 提供了一种用于监测指定集成电路内的温度的系统和方法。 有用地，系统包括靠近集成电路的至少一个振荡器装置，用于以与振荡器装置相邻的温度变化的频率产生信号脉冲。 该系统还包括控制单元，用于基于时不变参考时钟建立不变时间持续时间的采样周期。 一个采样分量被耦合以对在时间不变样本采集周期中的每一个期间由振荡器装置产生的脉冲数进行计数，并且对于连续的采样采集周期响应于各个计数值的阈值分量提供了当在 至少一些计数值具有与预先指定的过高温度水平相关联的值。
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3.发明授权Dynamic silicon characterization observability using functional clocks for system or run-time process characterization 失效使用功能时钟进行系统或运行时过程表征的动态硅表征可观察性公开(公告)号：US07164264B2
公开(公告)日：2007-01-16
申请号：US11055045
申请日：2005-02-10
IPC分类号： G01R31/26
CPC分类号： G06F11/24
摘要： A method and system for dynamic characterization observability using functional clocks for system or run-time process characterization. Silicon characterization circuitry may be read after silicon chips have been assembled in a package and installed in a system. A characterization circuit comprising one or more oscillators generates signal pulses, wherein the signal pulses represent a frequency of a circuit in the processor chip. A sampler circuit is connected to the characterization circuit, wherein the sampler circuit counts the number of the signal pulses from the characterization circuit within a predetermined time period. A control unit is connected to the sampler circuit, wherein the control unit comprises macros for collecting count data from the one or more oscillators to determine the silicon characterization. Based on the silicon characterization, the optimal operating frequency of the processor chip may be identified, as well as possible lifetime degradation of circuits on the chip.
摘要翻译： 使用功能时钟进行系统或运行时过程表征的动态表征可观察性的方法和系统。 硅片表征电路可以在硅芯片组装在封装中并安装在系统中之后被读取。 包括一个或多个振荡器的表征电路产生信号脉冲，其中信号脉冲表示处理器芯片中的电路的频率。 采样器电路连接到表征电路，其中采样器电路在预定时间段内对来自表征电路的信号脉冲的数量进行计数。 控制单元连接到采样器电路，其中控制单元包括用于收集来自一个或多个振荡器的计数数据的宏，以确定硅表征。 基于硅表征，可以识别处理器芯片的最佳工作频率，以及芯片上电路的可能的寿命衰退。
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公开(公告)号：US08312071B2
公开(公告)日：2012-11-13
申请号：US12101734
申请日：2008-04-11
IPC分类号： G06F7/58
摘要： A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.
摘要翻译： 随机数生成器包括公平校验器和校正模块，其确保在随机数发生器内将在预定时间段内的完整随机序列输出。
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5.发明授权Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法公开(公告)号：US07418541B2
公开(公告)日：2008-08-26
申请号：US11055404
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。
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6.发明授权公开(公告)号：US08090823B2
公开(公告)日：2012-01-03
申请号：US12259942
申请日：2008-10-28
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： G06F15/173 , G06F15/167
CPC分类号： G06F15/161
摘要： Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.
摘要翻译： 说明性实施例公开了提供对带内和带外固件的低级硬件访问的数据处理系统。 数据处理系统包括多个芯片，其包括至少一个处理器芯片和多个支持芯片。 至少一个处理器芯片包括使用现场可更换单元支持接口串行传输协议与多个支持芯片进行通信的现场可更换单元支持接口主机。 多个支持芯片中的每一个包括现场可更换单元支持接口从机，其中包括处理器的多个芯片中的一个包括现场可更换单元支持接口主机，以及不包括的多个芯片中的一个 处理器仅包括现场可更换单元支持接口从站。 只有现场可更换单元支持接口主机具有转换逻辑。
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公开(公告)号：US06662133B2
公开(公告)日：2003-12-09
申请号：US09798291
申请日：2001-03-01
申请人： Christopher John Engel , Norman Karl James , Brian Chan Monwai , Kevin F. Reick , Philip George Shephard, III , Marco Zamora
发明人： Christopher John Engel , Norman Karl James , Brian Chan Monwai , Kevin F. Reick , Philip George Shephard, III , Marco Zamora
IPC分类号： G06F11277
CPC分类号： G06F11/2236
摘要： Repairing arrays on a processor with an on chip built in self test engine on the processor is provided. A subset of the arrays is selected for testing. Data patterns are sent from the test engine to the subset of arrays at a plurality of operating parameters. A response is received at the test engine from the subset of arrays at the operating parameters. The received response is compared to an expected response using the test engine, wherein the processor controller determines if additional test failures were detected by the test engine for the subset of arrays with a plurality of JTAG based instructions. Code in the processor controller then determines the states that need to be scanned into the scannable latches to force the array control logic to choose additional spare wordlines and/or bitlines to repair the newly identified failures in addition to all previously defined repair actions.
摘要翻译： 提供了在处理器上修复阵列，内置了处理器内置的自检引擎。 选择一组数组进行测试。 数据模式在多个操作参数下从测试引擎发送到阵列子集。 在测试引擎处从操作参数的阵列子集接收到响应。 将接收到的响应与使用测试引擎的预期响应进行比较，其中处理器控制器确定测试引擎是否针对具有多个基于JTAG的指令的阵列子集检测到附加测试失败。 然后，处理器控制器中的代码确定需要扫描到可扫描锁存器中的状态，以强制阵列控制逻辑选择额外的备用字线和/或位线，以修复除了所有先前定义的修复动作之外的新识别的故障。
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8.发明申请Method for Providing Low-Level Hardware Access to In-Band and Out-of-Band Firmware 失效提供低级硬件访问带内和带外固件的方法公开(公告)号：US20090055563A1
公开(公告)日：2009-02-26
申请号：US12259942
申请日：2008-10-28
申请人： James Stephen Fields, JR. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, JR. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： G06F13/42
CPC分类号： G06F15/161
摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.
摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。
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9.发明申请Method for Indirect Access to a Support Interface for Memory-Mapped Resources to Reduce System Connectivity From Out-of-Band Support Processor 失效用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法公开(公告)号：US20080247415A1
公开(公告)日：2008-10-09
申请号：US12139631
申请日：2008-06-16
申请人： James Stephen Fields , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： H04L12/66
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。
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公开(公告)号：US20090282178A1
公开(公告)日：2009-11-12
申请号：US12118211
申请日：2008-05-09
IPC分类号： G06F13/18
CPC分类号： G06F13/364
摘要： A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.
摘要翻译： 用于形式验证伪随机数生成器和使用随机优先级仲裁方案的仲裁器的有界公平属性的系统。 形式验证系统根据完整随机序列的数量确定仲裁者的请求授权延迟的上限。 形式验证系统还根据多个时钟周期确定由仲裁器使用的随机数发生器产生的随机数序列中的完整随机序列的长度的上限和下限。 然后，形式验证系统通过将仲裁者的请求授权延迟的上限与上限结合来确定在多个时钟周期方面仲裁系统的最差情况请求授权延迟范围 的完整随机序列的长度和完整随机序列的长度的下限。
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