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    Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface
    1.
    发明授权
    Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface 失效
    具有存储块的半导体集成电路器件和能够存储来自外部接口的写入数据的写入缓冲器

    公开(公告)号：US06714477B2

    公开(公告)日：2004-03-30

    申请号：US10187947

    申请日：2002-07-03

    申请人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

    发明人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

    IPC分类号： G11C800

    CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4093

    摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

    摘要翻译： 读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置， 输出无能力状态不存在。 这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此 提高读取数据输出操作的吞吐量。

    Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting
    2.
    发明授权
    Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting 失效
    具有存储体的半导体集成电路装置和能够在另一存储体的数据输出时存储从一个存储体读出的数据的读取缓冲器

    公开(公告)号：US06430103B2

    公开(公告)日：2002-08-06

    申请号：US09775544

    申请日：2001-02-05

    申请人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

    发明人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

    IPC分类号： G11C800

    CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4093

    摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

    摘要翻译： 读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置， 输出无能力状态不存在。 这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此 提高读取数据输出操作的吞吐量。

    Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers
    3.
    发明授权
    Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers 有权
    半导体集成电路器件具有连接在主放大器的电源线之间的稳定电容器

    公开(公告)号：US06191990B1

    公开(公告)日：2001-02-20

    申请号：US09507785

    申请日：2000-02-22

    申请人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

    发明人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

    IPC分类号： G11C702

    CPC分类号： G11C7/18 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/11 ,  H01L28/75

    摘要： A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

    摘要翻译： 一种半导体集成电路器件具有存储器阵列，该存储器阵列包括将读出放大器中的动态存储单元读出的小电压放大到位线和选择位线的列开关MOSFET的读出放大器的MOSFET，包括用于读出的主放大器的读/写部分 来自由列开关选择的存储器单元的存储数据，以及实现与读/写部分的数据的输入/输出操作的逻辑电路。 两个电容器具有第一电极，其对应于具有与动态存储单元的存储电容器相同结构的平板电极的第一电极和作为存储电容器的多个共同连接的存储节点的第二电极串联连接设置 到读/写部分，并连接在读/写部分的操作电压线之间。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07078928B2

    公开(公告)日：2006-07-18

    申请号：US10736673

    申请日：2003-12-17

    申请人： Ryusuke Sahara ,  Kozaburo Kurita ,  Yuuji Suzuki ,  Mitsugu Kusunoki ,  Hideki Sakakibara

    发明人： Ryusuke Sahara ,  Kozaburo Kurita ,  Yuuji Suzuki ,  Mitsugu Kusunoki ,  Hideki Sakakibara

    IPC分类号： H03K19/00 ,  G01R31/28 ,  H03H11/26

    CPC分类号： G01R31/318577

    摘要： The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

    摘要翻译： 本发明提供一种配备有至少一个脉冲发生器的半导体集成电路器件，该脉冲发生器产生的脉冲脉冲短于传输信号的全幅度的上升时间。 通过第一信号路径和第二信号路径从外部提供的第一信号和第二信号分别传送到脉冲发生器。 当在第一信号路径和第二信号路径中的任何一个缓冲器上的上升时间达到全幅度时，脉冲发生器将形成的脉冲的脉冲宽度大于第一信号与第二信号路径之间的相位差 使第二信号对应于第一脉冲的脉冲宽度。