公开(公告)号：US08816733B2

公开(公告)日：2014-08-26

申请号：US12379727

申请日：2009-02-27

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03L7/06 ,  H03L7/081 ,  H03L7/093

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/093

摘要： A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.

摘要翻译： 延迟锁定环电路包括：检测外部时钟和内部时钟之间的相位差的相位比较器; 上/下计数器根据来自相位比较器的输出信号控制延迟时间; 以及延迟线，包括对应于从上/下计数器输出的信号的多个比特的多个单位延迟电路，以便控制外部时钟的延迟以使外部时钟符合内部时钟，并且其中单位延迟电路 在多个单元延迟电路的串联连接中，来自上/下计数器的输出中的同一位的输出控制不相互连接。

公开(公告)号：US08223239B2

公开(公告)日：2012-07-17

申请号：US12248992

申请日：2008-10-10

申请人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

发明人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

IPC分类号： H04N5/335

CPC分类号： H04N5/335 ,  G09G3/20 ,  G09G5/008 ,  G09G2300/0408 ,  G09G2310/08 ,  H03L7/0812 ,  H03L7/0814 ,  H04N5/3765

摘要： A clock signal generation circuit of a delay locked loop type includes a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected.

摘要翻译： 延迟锁定环路的时钟信号产生电路包括：延迟线，被配置为延迟第一时钟信号以产生第二时钟信号; 延迟量控制器，被配置为以所述第二时钟信号的相位与所述第一时钟信号的相位同步的方式改变所述延迟线中的延迟量; 伪锁定检测部，被配置为检测第一时钟信号和第二时钟信号的伪锁定状态; 以及伪锁定状态释放部，被配置为在检测到伪锁定状态的情况下改变延迟线的延迟量。

公开(公告)号：US07973581B2

公开(公告)日：2011-07-05

申请号：US12379019

申请日：2009-02-11

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03K3/356

CPC分类号： H03K3/356121 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091

摘要： A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.

摘要翻译： 触发器电路包括：接收数据信号的输入和上升延迟时钟信号的第一锁存电路，根据上升延迟时钟信号的下降而升高第一节点的信号，并降低第一 节点根据上升延时时钟信号的上升; 第二锁存电路，其在所述时钟信号下降的定时接收所述第一节点的信号的输入和所述时钟信号，并降低第二节点的信号; 第三锁存电路，其接收所述第二节点的信号的输入和所述时钟信号，并产生用于维持所述数据信号的输出信号; 以及下拉电路，其利用上升延迟时钟信号来拉低第一节点的信号。

公开(公告)号：US20090243678A1

公开(公告)日：2009-10-01

申请号：US12379727

申请日：2009-02-27

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/093

摘要： A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.

摘要翻译： 延迟锁定环电路包括：检测外部时钟和内部时钟之间的相位差的相位比较器; 上/下计数器根据来自相位比较器的输出信号控制延迟时间; 以及延迟线，包括对应于从上/下计数器输出的信号的多个比特的多个单位延迟电路，以便控制外部时钟的延迟以使外部时钟符合内部时钟，并且其中单位延迟电路 在多个单元延迟电路的串联连接中，由来自递增/递减计数器的输出中相同位的输出控制不相互连接。

公开(公告)号：US20090096906A1

公开(公告)日：2009-04-16

申请号：US12248992

申请日：2008-10-10

申请人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

发明人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

IPC分类号： H04N5/335 ,  G09G5/00 ,  H03L7/06

CPC分类号： H04N5/335 ,  G09G3/20 ,  G09G5/008 ,  G09G2300/0408 ,  G09G2310/08 ,  H03L7/0812 ,  H03L7/0814 ,  H04N5/3765

摘要： A clock signal generation circuit of a delay locked loop type includes a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected.

摘要翻译： 延迟锁定环路的时钟信号产生电路包括：延迟线，被配置为延迟第一时钟信号以产生第二时钟信号; 延迟量控制器，被配置为以所述第二时钟信号的相位与所述第一时钟信号的相位同步的方式改变所述延迟线中的延迟量; 伪锁定检测部，被配置为检测第一时钟信号和第二时钟信号的伪锁定状态; 以及伪锁定状态释放部，被配置为在检测到伪锁定状态的情况下改变延迟线的延迟量。

公开(公告)号：US20090219068A1

公开(公告)日：2009-09-03

申请号：US12379019

申请日：2009-02-11

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03L7/06 ,  H03K3/00

CPC分类号： H03K3/356121 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091

摘要： A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.

摘要翻译： 触发器电路包括：接收数据信号的输入和上升延迟时钟信号的第一锁存电路，根据上升延迟时钟信号的下降而升高第一节点的信号，并降低第一 节点根据上升延时时钟信号的上升; 第二锁存电路，其在所述时钟信号下降的定时接收所述第一节点的信号的输入和所述时钟信号，并降低第二节点的信号; 第三锁存电路，其接收所述第二节点的信号的输入和所述时钟信号，并产生用于维持所述数据信号的输出信号; 以及下拉电路，其利用上升延迟时钟信号来拉低第一节点的信号。

公开(公告)号：US07944259B2

公开(公告)日：2011-05-17

申请号：US12327878

申请日：2008-12-04

申请人： Michiru Senda ,  Hiroshi Mizuhashi

发明人： Michiru Senda ,  Hiroshi Mizuhashi

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G09G3/2096 ,  G09G5/008 ,  G09G2300/0426 ,  G09G2310/0291 ,  G09G2330/021 ,  H03L7/0812 ,  H03L7/0818 ,  H03L7/0891

摘要： A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion/non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation.

摘要翻译： 延迟同步环路型时钟信号发生电路包括：延迟线，用于将第一时钟信号延迟设定的延迟量并输出; 延迟时间长度设定单元，用于基于从输出端子输出的第二时钟信号与第一时钟信号之间的相位差设置延迟线的延迟时间长度; 相位关系确定单元，用于确定第一时钟信号和第二时钟信号的相位关系是否处于特定的相位关系; 以及在检测到特定相位关系时在包括延迟线的传输路径上执行第一时钟信号的相位反转的相位反转/非反转单元。

公开(公告)号：US07880519B2

公开(公告)日：2011-02-01

申请号：US12327893

申请日：2008-12-04

申请人： Michiru Senda ,  Hiroshi Mizuhashi

发明人： Michiru Senda ,  Hiroshi Mizuhashi

IPC分类号： H03L7/00

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/10

摘要： A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal.

摘要翻译： 延迟同步环路型时钟信号发生电路包括：数字延迟线，用于延迟第一时钟信号并产生第二时钟信号; 环型移位寄存器，用于通过其各级的触发器输出来设置数字延迟线的延迟时间长度; 以及延迟量控制单元，用于基于第一时钟信号和第二时钟信号之间的相位关系来控制向环型移位寄存器的移位时钟的提供。

公开(公告)号：US20090146711A1

公开(公告)日：2009-06-11

申请号：US12327878

申请日：2008-12-04

申请人： Michiru Senda ,  Hiroshi Mizuhashi

发明人： Michiru Senda ,  Hiroshi Mizuhashi

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G09G3/2096 ,  G09G5/008 ,  G09G2300/0426 ,  G09G2310/0291 ,  G09G2330/021 ,  H03L7/0812 ,  H03L7/0818 ,  H03L7/0891

摘要： A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion/non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation.

摘要翻译： 延迟同步环路型时钟信号发生电路包括：延迟线，用于将第一时钟信号延迟设定的延迟量并输出; 延迟时间长度设定单元，用于基于从输出端子输出的第二时钟信号与第一时钟信号之间的相位差设置延迟线的延迟时间长度; 相位关系确定单元，用于确定第一时钟信号和第二时钟信号的相位关系是否处于特定的相位关系; 以及在检测到特定相位关系时在包括延迟线的传输路径上执行第一时钟信号的相位反转的相位反转/非反转单元。

公开(公告)号：US20090146713A1

公开(公告)日：2009-06-11

申请号：US12327893

申请日：2008-12-04

申请人： Michiru Senda ,  Hiroshi Mizuhashi

发明人： Michiru Senda ,  Hiroshi Mizuhashi

IPC分类号： H03L7/00

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/10

摘要： A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal.

摘要翻译： 延迟同步环路型时钟信号发生电路包括：数字延迟线，用于延迟第一时钟信号并产生第二时钟信号; 环型移位寄存器，用于通过其各级的触发器输出来设置数字延迟线的延迟时间长度; 以及延迟量控制单元，用于基于第一时钟信号和第二时钟信号之间的相位关系来控制向环型移位寄存器的移位时钟的提供。