公开(公告)号：US08816733B2

公开(公告)日：2014-08-26

申请号：US12379727

申请日：2009-02-27

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03L7/06 ,  H03L7/081 ,  H03L7/093

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/093

摘要： A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.

摘要翻译： 延迟锁定环电路包括：检测外部时钟和内部时钟之间的相位差的相位比较器; 上/下计数器根据来自相位比较器的输出信号控制延迟时间; 以及延迟线，包括对应于从上/下计数器输出的信号的多个比特的多个单位延迟电路，以便控制外部时钟的延迟以使外部时钟符合内部时钟，并且其中单位延迟电路 在多个单元延迟电路的串联连接中，来自上/下计数器的输出中的同一位的输出控制不相互连接。

公开(公告)号：US20090219068A1

公开(公告)日：2009-09-03

申请号：US12379019

申请日：2009-02-11

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03L7/06 ,  H03K3/00

CPC分类号： H03K3/356121 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091

摘要： A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.

摘要翻译： 触发器电路包括：接收数据信号的输入和上升延迟时钟信号的第一锁存电路，根据上升延迟时钟信号的下降而升高第一节点的信号，并降低第一 节点根据上升延时时钟信号的上升; 第二锁存电路，其在所述时钟信号下降的定时接收所述第一节点的信号的输入和所述时钟信号，并降低第二节点的信号; 第三锁存电路，其接收所述第二节点的信号的输入和所述时钟信号，并产生用于维持所述数据信号的输出信号; 以及下拉电路，其利用上升延迟时钟信号来拉低第一节点的信号。

公开(公告)号：US08223239B2

公开(公告)日：2012-07-17

申请号：US12248992

申请日：2008-10-10

申请人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

发明人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

IPC分类号： H04N5/335

CPC分类号： H04N5/335 ,  G09G3/20 ,  G09G5/008 ,  G09G2300/0408 ,  G09G2310/08 ,  H03L7/0812 ,  H03L7/0814 ,  H04N5/3765

摘要： A clock signal generation circuit of a delay locked loop type includes a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected.

摘要翻译： 延迟锁定环路的时钟信号产生电路包括：延迟线，被配置为延迟第一时钟信号以产生第二时钟信号; 延迟量控制器，被配置为以所述第二时钟信号的相位与所述第一时钟信号的相位同步的方式改变所述延迟线中的延迟量; 伪锁定检测部，被配置为检测第一时钟信号和第二时钟信号的伪锁定状态; 以及伪锁定状态释放部，被配置为在检测到伪锁定状态的情况下改变延迟线的延迟量。

公开(公告)号：US07973581B2

公开(公告)日：2011-07-05

申请号：US12379019

申请日：2009-02-11

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03K3/356

CPC分类号： H03K3/356121 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091

摘要： A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.

摘要翻译： 触发器电路包括：接收数据信号的输入和上升延迟时钟信号的第一锁存电路，根据上升延迟时钟信号的下降而升高第一节点的信号，并降低第一 节点根据上升延时时钟信号的上升; 第二锁存电路，其在所述时钟信号下降的定时接收所述第一节点的信号的输入和所述时钟信号，并降低第二节点的信号; 第三锁存电路，其接收所述第二节点的信号的输入和所述时钟信号，并产生用于维持所述数据信号的输出信号; 以及下拉电路，其利用上升延迟时钟信号来拉低第一节点的信号。

公开(公告)号：US20090243678A1

公开(公告)日：2009-10-01

申请号：US12379727

申请日：2009-02-27

申请人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

发明人： Hiroshi Mizuhashi ,  Michiru Senda ,  Gen Koide

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/093

摘要： A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.

摘要翻译： 延迟锁定环电路包括：检测外部时钟和内部时钟之间的相位差的相位比较器; 上/下计数器根据来自相位比较器的输出信号控制延迟时间; 以及延迟线，包括对应于从上/下计数器输出的信号的多个比特的多个单位延迟电路，以便控制外部时钟的延迟以使外部时钟符合内部时钟，并且其中单位延迟电路 在多个单元延迟电路的串联连接中，由来自递增/递减计数器的输出中相同位的输出控制不相互连接。

公开(公告)号：US20090096906A1

公开(公告)日：2009-04-16

申请号：US12248992

申请日：2008-10-10

申请人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

发明人： Michiru Senda ,  Hiroshi Mizuhashi ,  Gen Koide

IPC分类号： H04N5/335 ,  G09G5/00 ,  H03L7/06

CPC分类号： H04N5/335 ,  G09G3/20 ,  G09G5/008 ,  G09G2300/0408 ,  G09G2310/08 ,  H03L7/0812 ,  H03L7/0814 ,  H04N5/3765

摘要： A clock signal generation circuit of a delay locked loop type includes a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected.

摘要翻译： 延迟锁定环路的时钟信号产生电路包括：延迟线，被配置为延迟第一时钟信号以产生第二时钟信号; 延迟量控制器，被配置为以所述第二时钟信号的相位与所述第一时钟信号的相位同步的方式改变所述延迟线中的延迟量; 伪锁定检测部，被配置为检测第一时钟信号和第二时钟信号的伪锁定状态; 以及伪锁定状态释放部，被配置为在检测到伪锁定状态的情况下改变延迟线的延迟量。

公开(公告)号：US09932705B2

公开(公告)日：2018-04-03

申请号：US13634672

申请日：2011-03-09

申请人： Gen Koide ,  Katsufumi Yanai

发明人： Gen Koide ,  Katsufumi Yanai

IPC分类号： D06N3/00 ,  D06N3/14 ,  C08J9/00 ,  C08J9/06

CPC分类号： D06N3/0004 ,  C08J9/0085 ,  C08J9/06 ,  C08J2205/044 ,  C08J2375/04 ,  D06N3/005 ,  D06N3/14 ,  D06N2205/023 ,  D06N2205/04 ,  D06N2205/243 ,  D06N2211/10 ,  D06N2211/14 ,  D06N2211/261 ,  D06N2211/28

摘要： Disclosed is a sheet-like material which is produced by an environmentally friendly procedure and has an elegant appearance with piloerection, good wear resistance and good texture. Specifically disclosed is a sheet-like material containing a water-dispersed polyurethane within a fibrous base that contains extra-fine fibers having an average single fiber diameter of 0.3-7 um. The inside of the water-dispersed polyurethane is provided with pores each having a diameter of 10-200 um. Also specifically disclosed is a method for producing a sheet-like material by applying a polyurethane liquid to a fibrous base, wherein the polyurethane liquid is a water-dispersed polyurethane liquid that contains a foaming agent and a dry film of the polyurethane that constitutes the polyurethane liquid has a 100% modulus of 3-8 MPa.

公开(公告)号：US20130005848A1

公开(公告)日：2013-01-03

申请号：US13634672

申请日：2011-03-09

申请人： Gen Koide ,  Katsufumi Yanai

发明人： Gen Koide ,  Katsufumi Yanai

IPC分类号： C08K7/02 ,  C08L75/04

CPC分类号： D06N3/0004 ,  C08J9/0085 ,  C08J9/06 ,  C08J2205/044 ,  C08J2375/04 ,  D06N3/005 ,  D06N3/14 ,  D06N2205/023 ,  D06N2205/04 ,  D06N2205/243 ,  D06N2211/10 ,  D06N2211/14 ,  D06N2211/261 ,  D06N2211/28

摘要： Disclosed is a sheet-like material which is produced by an environmentally friendly procedure and has an elegant appearance with piloerection, good wear resistance and good texture. Specifically disclosed is a sheet-like material containing a water-dispersed polyurethane within a fibrous base that contains extra-fine fibers having an average single fiber diameter of 0.3-7 um. The inside of the water-dispersed polyurethane is provided with pores each having a diameter of 10-200 um. Also specifically disclosed is a method for producing a sheet-like material by applying a polyurethane liquid to a fibrous base, wherein the polyurethane liquid is a water-dispersed polyurethane liquid that contains a foaming agent and a dry film of the polyurethane that constitutes the polyurethane liquid has a 100% modulus of 3-8 MPa.

摘要翻译： 公开了一种片状材料，其通过环境友好的方法制造，具有优雅的外观，具有良好的耐磨性和良好的质感。 具体公开了一种片状材料，其含有在纤维基体内的水分散性聚氨酯，其含有平均单纤维直径为0.3-7μm的超细纤维。 水分散聚氨酯的内部设有直径为10-200μm的孔。 还具体公开了一种通过将聚氨酯液体涂布在纤维基材上来制造片状材料的方法，其中聚氨酯液体是含有发泡剂的水分散聚氨酯液体和构成聚氨酯的聚氨酯的干膜 液体的100％模量为3-8MPa。

公开(公告)号：US07592055B2

公开(公告)日：2009-09-22

申请号：US10542594

申请日：2004-01-29

申请人： Keiji Takeda ,  Gen Koide

发明人： Keiji Takeda ,  Gen Koide

IPC分类号： B65B53/00 ,  B32B27/12

CPC分类号： B32B27/12 ,  B32B5/022 ,  B32B7/12 ,  B32B27/08 ,  B32B27/10 ,  B32B2307/724 ,  B32B2307/7265 ,  B32B2419/00 ,  B32B2437/00 ,  B32B2607/02 ,  C08G18/0823 ,  C08G18/3212 ,  C08G18/44 ,  C08G18/4833 ,  C08G18/4854 ,  C08J7/047 ,  C08J2367/02 ,  C08J2377/00 ,  C08J2475/00 ,  C08K3/36 ,  C08L67/00 ,  C08L75/04 ,  C09D175/04 ,  Y10T428/1331 ,  Y10T428/31551 ,  Y10T442/674 ,  C08L2666/18 ,  C08L2666/16 ,  C08L2666/54 ,  C08L2666/20

摘要： This invention provides a moisture-permeable, waterproof film characterized in that it consists of two or more resin layers comprising, as polymerizing components, bishidroxyalkyl aliphatic acid and alkyleneglycol, said bishydroxyalkyl aliphatic acid content is 0.08 mmol/g to 0.5 mmol/g, at least a part of said alykyleneglycol is polyethylene glycol contained in an amount of 40 wt % to 80 wt % based on said solid resin, and a moisture permeability by JIS L-1099 “Potassium Acetate Method” (B-1 method) at average film thickness of 20 micrometers being not less than 3×103 g/m2·24 h and not more than 200×103 g/m2·24 h, and a moisture-permeable waterproof composite material to which said moisture-permeable, waterproof film is provided at least on one surface of a substrate material and its moisture permeability by JIS L-1099 “Potassium Acetate Method” (B-1 method) being not less than 1×103 g/m2·24 h and not more than 50×103 g/m2·24 h.This invention makes use of a polymer having excellent moisture permeability, waterproofness durability and capability of being made aqueous, and accordingly, this invention provides a moisture-permeable, waterproof film and a composite material which can be manufactured by an ecological process.

摘要翻译： 本发明提供一种透湿性防水膜，其特征在于，其由两个或更多个树脂层组成，所述树脂层包含作为聚合组分的双烷氧基烷基脂肪酸和亚烷基二醇，所述双羟烷基脂肪酸含量为0.08mmol / g至0.5mmol / g， 所述亚烷基二醇的至少一部分为聚乙二醇，其含量相对于所述固体树脂为40重量％〜80重量％，平均膜为JIS L-1099“醋酸钾法”（B-1法） 20微米的厚度不小于3×10 3 g / m 2·24小时，不大于200×10 3 g / m 2·24小时;以及透湿性防水复合材料，所述透湿防水膜至少设置在一个 基板材料的表面和通过JIS L-1099“乙酸钾法”（B-1法）的透湿度不小于1×103g / m 2·24h，不大于50×103g / m 2·24h。 本发明利用具有优异的透湿性，防水性和耐水性的聚合物，因此，本发明提供了一种可通过生态工艺制造的透湿防水膜和复合材料。

公开(公告)号：US20150348489A1

公开(公告)日：2015-12-03

申请号：US14716240

申请日：2015-05-19

申请人： Masaaki Kabe ,  Hiroki Uchiyama ,  Toshiaki Fukushima ,  Gen Koide

发明人： Masaaki Kabe ,  Hiroki Uchiyama ,  Toshiaki Fukushima ,  Gen Koide

IPC分类号： G09G3/36 ,  G09G5/18

CPC分类号： G09G3/3696 ,  G09G3/20 ,  G09G3/2003 ,  G09G3/3614 ,  G09G5/18 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0465 ,  G09G2330/021 ,  G09G2340/0457

摘要： A display device includes an image display panel and a control device. The image display panel includes first sub-pixels, second sub-pixels, third sub-pixels, and fourth sub-pixels in which a specified sub-pixel column including the third sub-pixels and the fourth sub-pixels and at least one other sub-pixel column arranged next to the specified sub-pixel column are periodically arranged. The control device performs column inversion driving to apply a voltage having the same polarity to signal lines of a first specified sub-pixel column belonging to the specified sub-pixel columns and the other sub-pixel column adjacent to the first specified sub-pixel column, apply a voltage having the same polarity as the first specified sub-pixel column to one of the signal lines of a second specified sub-pixel column and a third specified sub-pixel column adjacent to the first specified sub-pixel column, and invert the polarities of the voltages to be applied at predetermined cycles.

摘要翻译： 显示装置包括图像显示面板和控制装置。 图像显示面板包括第一子像素，第二子像素，第三子像素和第四子像素，其中包括第三子像素和第四子像素的指定子像素列和至少一个其他子像素 周期性地布置了排列在指定的子像素列旁边的子像素列。 控制装置进行列反转驱动，对属于指定子像素列的第一指定子像素列和与第一指定子像素列相邻的另一子像素列的信号线施加具有相同极性的电压 将与第一指定子像素列具有相同极性的电压施加到与第一指定子像素列相邻的第二指定子像素列和第三指定子像素列的信号线之一，并且反转 以预定周期施加的电压的极性。