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1.发明授权System and method for allocating and sharingpage buffers for a flash memory device 失效用于分配和共享闪存设备的页缓冲器的系统和方法
公开(公告)号：US5802552A
公开(公告)日：1998-09-01
申请号：US942187
申请日：1997-10-01
CPC分类号： G06F12/0638 , G06F2212/2022
摘要： A flash memory device having a page buffer circuit providing a shared resource between a flash array controller circuit and a user. The page buffer circuit comprises a Plane A and a Plane B, wherein each of the planes A and B is a static random access memory array. The page buffer circuit further comprises a mode control circuit for enabling access to the planes A and B over a host bus in a user mode and access to the planes A and B by the flash array controller in a flash array controller mode.
摘要翻译： 一种具有在闪存阵列控制器电路和用户之间提供共享资源的页面缓冲电路的闪存设备。 页面缓冲电路包括平面A和平面B，其中平面A和B中的每一个是静态随机存取存储器阵列。 页面缓冲电路还包括模式控制电路，用于通过主机总线以用户模式访问平面A和B，并且以闪存阵列控制器模式通过闪存阵列控制器访问平面A和B.
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2.发明授权
公开(公告)号：US5623620A
公开(公告)日：1997-04-22
申请号：US85542
申请日：1993-06-30
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译： 一种具有特殊测试模式的页面缓冲电路的闪存设备。 页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。 页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。 页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。
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3.发明授权
公开(公告)号：US5835927A
公开(公告)日：1998-11-10
申请号：US719583
申请日：1996-09-25
IPC分类号： G01R31/3185 , G06F11/22 , G06F12/02 , G11C11/00 , G11C16/10 , G11C29/26 , G11C29/48 , G06F12/00
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译： 一种具有特殊测试模式的页面缓冲电路的闪存设备。 页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。 页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。 页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。
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公开(公告)号：US5430677A
公开(公告)日：1995-07-04
申请号：US239939
申请日：1994-05-09
申请人： Mickey L. Fandrich , Owen Jungroth
发明人： Mickey L. Fandrich , Owen Jungroth
摘要： In a memory array having a plurality of rows and columns of memory devices for storing binary conditions, apparatus for selecting particular memory devices, a sense amplifier for transferring indications of the conditions of selected memory devices, and apparatus for generating signals indicative of conditions other than the state of the memory devices, the improvement including a multiplexor, the multiplexor being arranged to accept as input the output of the sense amplifier and the signals indicative of conditions other than the state of the memory devices, the multiplexor and the apparatus for generating signals indicative of conditions other than the state of the memory devices being positioned in a manner that parasitic capacitance affecting the input to the sense amplifier is not created. The output of the sense amplifier may also be connected to other internal circuits so that the memory array may be accessed while bringing other signals to the output pins.
摘要翻译： 在具有用于存储二进制条件的存储器装置的多个行和列的存储器阵列中，用于选择特定存储器件的装置，用于传送所选择的存储器件的条件的指示的读出放大器，以及用于产生指示除了 所述存储器件的状态，所述改进包括多路复用器，所述多路复用器被布置为接受所述读出放大器的输出作为输入，以及指示所述存储器件状态以外的条件的信号，所述多路复用器和用于产生信号的装置 指示除了存储器件的状态之外的条件，其方式是不产生影响读出放大器的输入的寄生电容。 读出放大器的输出也可以连接到其他内部电路，使得可以访问存储器阵列，同时向输出引脚提供其他信号。
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5.发明授权Memory device with a central control bus and a control access register for translating an access request into an access cycle on the central control bus 失效具有中央控制总线和控制访问寄存器的存储器件，用于将访问请求转换为中央控制总线上的访问周期
公开(公告)号：US5748939A
公开(公告)日：1998-05-05
申请号：US601652
申请日：1996-02-14
摘要： A memory device includes a cell array having a plurality of memory cells and a read/write circuit having circuitry for selecting, writing, and reading the memory cells according to a plurality of control signals. A control register circuit is provided that has at least one control register coupled to communicate over a central control bus. A control access circuit is provided that receives an access request targeted for the control register, and translates the access request into an access cycle on the central control bus. The access cycle loads the control register and causes the control register circuit to generate the control signals. The control access circuit receives the access request targeted for the control register from an array controller circuit that generates the access request to load the control register and generate the control signals according to a user command received over a host bus. The control register includes an address decode circuit, a function decode circuit, a master data latch, a slave data latch, and a read control circuit.
摘要翻译： 存储器件包括具有多个存储单元的单元阵列和具有根据多个控制信号选择，写入和读取存储单元的电路的读/写电路。 提供了控制寄存器电路，其具有耦合以通过中央控制总线通信的至少一个控制寄存器。 提供控制访问电路，其接收针对控制寄存器的访问请求，并将访问请求转换为中央控制总线上的访问周期。 访问周期加载控制寄存器，并使控制寄存器电路产生控制信号。 控制访问电路从产生访问请求的阵列控制器电路接收控制寄存器的访问请求，以加载控制寄存器，并根据通过主机总线接收的用户命令生成控制信号。 控制寄存器包括地址解码电路，功能解码电路，主数据锁存器，从属数据锁存器和读控制电路。
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公开(公告)号：US5519847A
公开(公告)日：1996-05-21
申请号：US85969
申请日：1993-06-30
CPC分类号： G11C16/10 , G11C7/1039
摘要： A method of increasing the data throughput of a memory device including a page buffer. Data throughput is increased by pipelining write operations such that one plane of the page buffer is being used to program the memory array of the device while the other plane of the page buffer is being loaded with data to be used in the next program operation. The first write operation is set up by loading a first block of data in to the first plane of the page buffer. In the following clock cycle, the first operation begins by commanding the memory device to program the memory array with the first block of data stored in the first plane. The second write operation is setup immediately following the first command to program. The second write operation is setup by loading a second block of data into the second plane of the page buffer. Loading of the second plane occurs while the memory array is being programmed from the first plane. The second write operation begins by commanding the array controller to program the flash memory array with the second block of data stored in the second plane.
摘要翻译： 一种增加包括页面缓冲器的存储设备的数据吞吐量的方法。 通过流水线写入操作来增加数据吞吐量，使得页面缓冲器的一个平面被用于编程器件的存储器阵列，同时页面缓冲器的另一个平面被加载要在下一个程序操作中使用的数据。 第一个写入操作是通过将第一个数据块加载到页面缓冲区的第一个平面来设置的。 在下一个时钟周期中，第一个操作开始于命令存储器件对存储在第一平面中的第一数据块进行编程。 第二次写入操作是在第一个编程命令之后立即设置的。 通过将第二数据块加载到页面缓冲器的第二平面来设置第二写入操作。 当从第一平面编程存储器阵列时发生第二平面的加载。 第二次写操作开始于命令阵列控制器用存储在第二平面中的第二数据块对闪存阵列进行编程。
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7.发明授权
公开(公告)号：US5509134A
公开(公告)日：1996-04-16
申请号：US86186
申请日：1993-06-30
CPC分类号： G06F9/4812 , G06F9/45512 , G11C16/10
摘要： A flash memory system includes a user interface and array controller. The user interface receives the user command issued by the processor and has the ability to queue a plurality of commands for execution. The user interface further functions as an arbiter to control the priority of commands to be executed. The array controller performs the operations on the flash array such as program and erase. The array controller consists of a general purpose processor with program memory which is programmable by the user. The program memory stores one or more algorithms that can be executed by the array controller. The algorithm is selected according to the command received at the user interface. The algorithms can be customized simply by programming the program memory. The system further provides an interrupt mechanism which enables the flash memory system to perform a context switch of a higher priority command with the lower priority, but currently executing, command.
摘要翻译： 闪存系统包括用户界面和阵列控制器。 用户接口接收由处理器发出的用户命令，并具有排队多个命令以执行的能力。 用户界面进一步充当仲裁器，以控制要执行的命令的优先级。 阵列控制器执行闪存阵列上的操作，如程序和擦除。 阵列控制器由具有可由用户编程的程序存储器的通用处理器组成。 程序存储器存储可由阵列控制器执行的一个或多个算法。 该算法根据用户界面接收到的命令进行选择。 可以通过编程程序存储器来简单地定制算法。 该系统进一步提供了一种中断机制，使得闪存系统能够执行具有较低优先级但当前执行命令的较高优先级命令的上下文切换。
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公开(公告)号：US06370651B1
公开(公告)日：2002-04-09
申请号：US08688235
申请日：1996-07-29
IPC分类号： G06F132
摘要： A method and apparatus for synchronizing a micro controller in a flash memory device. An interface circuit receives a user command over a host bus. A synchronizer circuit enables an oscillator circuit if the user command specifies an operation on a flash cell array. The oscillator circuit generates a clock signal for synchronizing the micro controller. After completion of the program or erase operation, the synchronizer circuit disables the oscillator circuit if a subsequent user command that specifies another program or erase operation for the micro controller is not pending.
摘要翻译： 一种用于在闪存设备中同步微控制器的方法和装置。 接口电路通过主机总线接收用户命令。 如果用户命令指定闪存单元阵列上的操作，则同步器电路使能振荡器电路。 振荡器电路产生用于使微控制器同步的时钟信号。 在完成编程或擦除操作之后，如果为微控制器指定另一程序或擦除操作的后续用户命令未被等待，则同步器电路禁用振荡器电路。
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公开(公告)号：US5692138A
公开(公告)日：1997-11-25
申请号：US754104
申请日：1996-11-21
CPC分类号： G06F13/1642 , G06F13/18 , G11C16/102
摘要： A flash memory device having a flash cell array comprising a plurality of flash cells, a flash array controller circuit for performing program and erase operations on the flash cell array according to a queue operation, and an interface circuit for generating the queue operation according to a user command and a set of command parameters received over a host bus. The interface circuit determines a set of limited resource control bits for the user command and queues the user command and associated parameters to the flash array controller circuit.
摘要翻译： 一种具有包括多个闪存单元的闪存单元阵列的闪速存储器件，用于根据队列操作对闪存单元阵列进行编程和擦除操作的闪存阵列控制器电路，以及用于根据队列操作产生队列操作的接口电路 用户命令和一组通过主机总线接收的命令参数。 接口电路确定用户命令的一组有限的资源控制位，并将用户命令和相关参数排队到闪存阵列控制器电路。
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10.发明授权Method and circuitry for queuing snooping, prioritizing and suspending commands 失效排队窥探，优先排序和挂起命令的方法和电路
公开(公告)号：US5559988A
公开(公告)日：1996-09-24
申请号：US408100
申请日：1995-03-21
CPC分类号： G06F3/0601 , G11C16/102 , G06F2003/0694
摘要： A method of, and apparatus for, storing and prioritizing among erase block and program word commands is described for a nonvolatile memory device. This prevents the depth of an operation queue responsible for queuing program and erase commands from limiting the number of erase commands that are stored at one time. The first erase command received serves as a place holder, holding a place within the operation queue for all subsequently received erase commands. All subsequently received erase commands are absorbed and cleared from the operation queue. As a result, the operation queue may receive additional commands and an erase command may be queued for every block of memory within the nonvolatile memory device. Absorbed erase commands can be prioritized in response to subsequently received program commands. Blocks are flagged for priority erasure using a priority register. Additionally, interrupt windows located at safe points permit interruption of erase operations to handle command interrupts. The erasure of one or more blocks can be suspended so that a program word command can be serviced thereby permitting program word commands to jump ahead of erase block commands in the queue. Furthermore, a query can be made to determine the status of any block and the block status query will consider pending commands in the operation queue when determining the block status for the block queried.
摘要翻译： 描述了用于非易失性存储器件的擦除块和程序字命令之间存储和优先化的方法和设备。 这样可以防止排队程序和擦除命令的操作队列的深度限制一次存储的擦除命令的数量。 接收到的第一个擦除命令用作占位符，在操作队列内保存所有随后接收到的擦除命令的位置。 所有随后接收到的擦除命令都被从操作队列中吸收和清除。 结果，操作队列可以接收附加命令，并且可以为非易失性存储器件内的每个存储器块排队擦除命令。 响应于随后接收到的程序命令，可以优先考虑吸收擦除命令。 使用优先级寄存器将块标记为优先擦除。 此外，位于安全点的中断窗口允许中断擦除操作以处理命令中断。 可以暂停一个或多个块的擦除，从而可以对程序字命令进行服务，从而允许程序字命令跳过队列中的擦除块命令。 此外，当确定所查询的块的块状态时，可以进行查询来确定任何块的状态，并且块状态查询将考虑在操作队列中的等待命令。
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