公开(公告)号：US20240079358A1

公开(公告)日：2024-03-07

申请号：US17939880

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Siva Sai Kishore Palli ,  Venkata Rama Satya Pradeep Vempaty ,  Wen How Sim ,  Chen Yu Huang ,  Harjashan Veer Singh

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05573 ,  H01L2224/16014 ,  H01L2224/1607 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/384

Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate and a die stack carried by the package substrate. The die stack can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die. The first semiconductor die can have an upper surface and a first bond pad carried by the upper surface that includes a curvilinear concave depression formed in an uppermost surface of the first bond pad. The second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The die stack can also include solder structure electrically coupling the first and second bond pads and at least partially filling the curvilinear concave depression formed in the uppermost surface of the first bond pad.

公开(公告)号：US20240071977A1

公开(公告)日：2024-02-29

申请号：US17823189

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Chen Yu Huang ,  Chong Leong Gan

IPC: H01L23/00 ,  H01L23/24 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/33 ,  H01L23/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/3128 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/33183 ,  H01L2224/33505 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83855 ,  H01L2924/0665

Abstract: A semiconductor package having a fillet is provided. The semiconductor package includes a trace disposed within a solder mask that has a top surface. A first die is over the solder mask and mechanically couples with the trace. A first adhesive is between the trace and the first die where sides of the first die and the first adhesive define a die edge. The semiconductor package includes a fillet adjacent the die edge and a second die above the first die. The semiconductor package also includes a second adhesive having a bottom surface where the second adhesive is between the first die and the second die. The solder mask top surface, the first die surface, and the second adhesive bottom surface define a cavity where the fillet is within the cavity at the die edge.

公开(公告)号：US20240347413A1

公开(公告)日：2024-10-17

申请号：US18605034

申请日：2024-03-14

Applicant: Micron Technology, Inc.

Inventor： Chen Yu Huang ,  Chong Leong Gan

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/373 ,  H01L23/3178 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/16 ,  H01L25/105 ,  H01L24/48 ,  H01L2224/05147 ,  H01L2224/16148 ,  H01L2224/48147 ,  H01L2224/48229 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/1431 ,  H10B80/00

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly can include a substrate and one or more semiconductor dies. The semiconductor device assembly can further include a thermally conductive material (e.g., carbon nanotubes, graphene) capable of dissipating heat from the semiconductor device assembly. In doing so, a thermally regulated semiconductor device can be assembled.