公开(公告)号：US20230176978A1

公开(公告)日：2023-06-08

申请号：US17541786

申请日：2021-12-03

申请人： Micron Technology, Inc.

发明人： Chung Kuang Chin ,  Di Hsien Ngu ,  Horia C. Simionescu

IPC分类号： G06F12/1009

CPC分类号： G06F12/1009 ,  G06F2212/651

摘要： Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.

公开(公告)号：US11494306B2

公开(公告)日：2022-11-08

申请号：US17003336

申请日：2020-08-26

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Chung Kuang Chin ,  Paul Stonelake ,  Narasimhulu Dharanikumar Kotte

IPC分类号： G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G11C14/00

摘要： Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.

公开(公告)号：US20240302958A1

公开(公告)日：2024-09-12

申请号：US18657466

申请日：2024-05-07

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Chung Kuang Chin

IPC分类号： G06F3/06 ,  G06F12/0802 ,  G06F12/10 ,  G06F12/123

CPC分类号： G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/10 ,  G06F12/124 ,  G06F12/0802 ,  G06F2212/452

摘要： Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

公开(公告)号：US20210089450A1

公开(公告)日：2021-03-25

申请号：US17003345

申请日：2020-08-26

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Chung Kuang Chin ,  Paul Stonelake ,  Narasimhulu Dharanikumar Kotte

IPC分类号： G06F12/084 ,  G06F13/16

摘要： Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.

公开(公告)号：US20210089449A1

公开(公告)日：2021-03-25

申请号：US17003336

申请日：2020-08-26

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Chung Kuang Chin ,  Paul Stonelake ,  Narasimhulu Dharanikumar Kotte

IPC分类号： G06F12/084 ,  G06F13/16

摘要： Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.

公开(公告)号：US20230176731A1

公开(公告)日：2023-06-08

申请号：US17543039

申请日：2021-12-06

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Chung Kuang Chin

IPC分类号： G06F3/06 ,  G06F12/10 ,  G06F12/123

CPC分类号： G06F3/0604 ,  G06F12/10 ,  G06F12/124 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/0802

摘要： Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

公开(公告)号：US12066949B2

公开(公告)日：2024-08-20

申请号：US17541786

申请日：2021-12-03

申请人： Micron Technology, Inc.

发明人： Chung Kuang Chin ,  Di Hsien Ngu ,  Horia C. Simionescu

IPC分类号： G06F12/1009

CPC分类号： G06F12/1009 ,  G06F2212/651 ,  G06F2212/7201

摘要： Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.

公开(公告)号：US11995314B2

公开(公告)日：2024-05-28

申请号：US17543039

申请日：2021-12-06

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Chung Kuang Chin

IPC分类号： G06F3/06 ,  G06F12/10 ,  G06F12/123 ,  G06F12/0802

CPC分类号： G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/10 ,  G06F12/124 ,  G06F12/0802 ,  G06F2212/452

摘要： Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

公开(公告)号：US11531622B2

公开(公告)日：2022-12-20

申请号：US17003345

申请日：2020-08-26

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Chung Kuang Chin ,  Paul Stonelake ,  Narasimhulu Dharanikumar Kotte

IPC分类号： G06F12/084 ,  G06F13/16 ,  G11C14/00

摘要： Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.

公开(公告)号：US20210089454A1

公开(公告)日：2021-03-25

申请号：US17003331

申请日：2020-08-26

申请人： Micron Technology, Inc.

发明人： Horia C. Simionescu ,  Paul Stonelake ,  Chung Kuang Chin ,  Narasimhulu Dharanikumar Kotte ,  Robert M. Walker ,  Cagdas Dirik

IPC分类号： G06F12/0817 ,  G06F12/0891 ,  G06F12/123 ,  G06F13/16

摘要： Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity.