公开(公告)号：US20130237056A1

公开(公告)日：2013-09-12

申请号：US13858800

申请日：2013-04-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Junting Liu-Norrod ,  Er-Xuan Ping ,  Seiichi Takedai

IPC: H01L21/768

CPC classification number: H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

Abstract: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Abstract translation: 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US08735292B2

公开(公告)日：2014-05-27

申请号：US13858800

申请日：2013-04-08

Applicant: Micron Technology, Inc.

Inventor： Junting Liu-Norrod ,  Er-Xuan Ping ,  Seiichi Takedai

IPC: H01L21/302

CPC classification number: H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

Abstract: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Abstract translation: 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US20130166057A1

公开(公告)日：2013-06-27

申请号：US13775878

申请日：2013-02-25

Applicant: Micron Technology, Inc.

Inventor： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  Cem Basceri ,  David J. Kubista

IPC: G05B19/00

CPC classification number: H01L28/40 ,  H01L21/3141 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/84

Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.

Abstract translation: 本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。 一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。 可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层 至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。 第二导电层可以与介电层接触并具有不大于约的厚度。