公开(公告)号：US11790995B2

公开(公告)日：2023-10-17

申请号：US17400924

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Vladimir Mikhalev

IPC: G11C16/04 ,  G11C16/14 ,  H01L29/735

CPC classification number: G11C16/14 ,  G11C16/0483 ,  H01L29/735

Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

公开(公告)号：US11756792B2

公开(公告)日：2023-09-12

申请号：US16899715

申请日：2020-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Violette ,  Vladimir Mikhalev

IPC: H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L21/027 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L21/266 ,  H01L21/26513 ,  H01L29/1095 ,  H01L29/66825 ,  H01L29/66833 ,  G11C16/0483 ,  G11C16/08 ,  H01L21/0274 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Transistors having a control gate isolated from a first region of semiconductor material having a first conductivity type, first and second source/drain regions having a second conductivity type different than the first conductivity type and formed in the first region of semiconductor material, and a second region of semiconductor material having the first conductivity type in contact with the first region of semiconductor material, wherein the first region of semiconductor material is between the control gate and the second region of semiconductor material, wherein the first region of semiconductor material has a first width, and wherein the second region of semiconductor material has a second width, less than or equal to the first width, as well as memory containing such transistors.

公开(公告)号：US20230046480A1

公开(公告)日：2023-02-16

申请号：US17400924

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Vladimir Mikhalev

IPC: G11C16/14 ,  G11C16/04 ,  H01L29/735

Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

公开(公告)号：US20220181341A1

公开(公告)日：2022-06-09

申请号：US17110439

申请日：2020-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu ,  Michael Violette ,  Mark A. Helm ,  Guangyu Huang ,  Vladimir Mikhalev

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  G11C16/04

Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.

公开(公告)号：US10727062B2

公开(公告)日：2020-07-28

申请号：US15892584

申请日：2018-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Violette ,  Vladimir Mikhalev

IPC: H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L21/027 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/08

Abstract: Methods of forming a portion of an integrated circuit include forming a patterned mask having an opening and exposing a surface of a semiconductor material, forming a first doped region at a first level of the semiconductor material through the opening, and isotropically removing a portion of the patterned mask to increase a width of the opening. The methods further include forming a second doped region at a second level of the semiconductor region through the opening after isotropically removing the portion of the patterned mask, wherein the second level is closer to the surface of the semiconductor material than the first level.

公开(公告)号：US20140339648A1

公开(公告)日：2014-11-20

申请号：US14448198

申请日：2014-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

Abstract: A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

Abstract translation: 晶体管包括在具有第一导电类型的半导体上的栅极电介质，栅极电介质上的控制栅极，在具有第一导电类型的半导体中具有第二导电类型的源极和漏极区域，以及具有第二导电类型的条带 半导体具有第一导电类型并且插入在控制栅极和源极和漏极区域中的至少一个之间。

公开(公告)号：US20240234311A1

公开(公告)日：2024-07-11

申请号：US18610267

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827 ,  H10B10/12

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

公开(公告)号：US20230017305A1

公开(公告)日：2023-01-19

申请号：US17730325

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Mattia Cichocki ,  Vladimir Mikhalev ,  Phani Bharadwaj Vanguri ,  James Eric Davis ,  Kenneth William Marr ,  Chiara Cerafogli ,  Michael James Irwin ,  Domenico Tuzi ,  Umberto Siciliani ,  Alessandro Alilla ,  Andrea Giovanni Xotta ,  Chung-Ping Wu ,  Luigi Marchese ,  Pasquale Conenna ,  Joonwoo Nam ,  Ishani Bhatt ,  Fulvio Rori ,  Andrea D'Alessandro ,  Michele Piccardi ,  Aleksey Prozapas ,  Luigi Pilolli ,  Violante Moschiano

IPC: H01L27/02 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

公开(公告)号：US20220319599A1

公开(公告)日：2022-10-06

申请号：US17223482

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Haitao Liu

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423

Abstract: Multi-gate transistors, as well as apparatus containing such multi-gate transistors and methods of forming such multi-gate transistors, might facilitate gating voltages in integrated circuit devices. Such multi-gate transistors might include an active area having a first conductivity type, a first source/drain region in the active area and having a second conductivity type different than the first conductivity type, a second source/drain region in the active area and having the second conductivity type, and a plurality of control gates adjacent the active area between the first source/drain region and the second source/drain region, wherein each control gate of the plurality of control gates comprises a respective plurality of control gate portions, and wherein, for a particular control gate of the plurality of control gates, each control gate portion of its respective plurality of control gate portions is adjacent the active area in a respective plane of a plurality of different planes.

公开(公告)号：US11063034B2

公开(公告)日：2021-07-13

申请号：US16454908

申请日：2019-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Michael Violette

IPC: H01L27/02 ,  H01L49/02 ,  H01L29/866 ,  H01L27/11526 ,  H01L29/45 ,  G11C16/30 ,  H01L27/11578 ,  H01L27/11551 ,  G11C16/04 ,  H01L27/11573 ,  H01L23/60 ,  H01L23/62 ,  G11C7/24

Abstract: Capacitor structures including a first island of a first conductive region and a second island of the first conductive region having a first conductivity type, an island of a second conductive region having a second conductivity type different than the first conductivity type, a dielectric overlying the first island of the first conductive region, a conductor overlying the dielectric, and a terminal of a diode overlying the second island of the first conductive region and overlying the island of the second conductive region.