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    Sequential voltage control for a memory device
    1.
    发明授权
    Sequential voltage control for a memory device 有权

    公开(公告)号：US11257549B2

    公开(公告)日：2022-02-22

    申请号：US16870670

    申请日：2020-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

    IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/417 ,  G11C16/30 ,  G11C16/12 ,  G11C7/20 ,  G11C16/04 ,  G11C16/32

    Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

    SYSTEMS AND METHODS FOR CONTROLLING COMMON MODE LEVEL FOR SENSE AMPLIFIER CIRCUITRY
    2.
    发明公开
    SYSTEMS AND METHODS FOR CONTROLLING COMMON MODE LEVEL FOR SENSE AMPLIFIER CIRCUITRY 审中-公开

    公开(公告)号：US20240055044A1

    公开(公告)日：2024-02-15

    申请号：US17884261

    申请日：2022-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam

    IPC: G11C11/4091

    CPC classification number: G11C11/4091

    Abstract: A memory device includes a memory cell that stores data. The memory device also includes a pair of digit lines that carry the data from the memory cell. The memory device further includes a sense amplifier that senses and amplifies voltages received at the pair of digit lines. The memory device also includes a replica sense amplifier that generates a replica common mode voltage associated with a common mode voltage of the pair of digit lines.

    Grouping power supplies for a sleep mode
    3.
    发明授权
    Grouping power supplies for a sleep mode 有权

    公开(公告)号：US11487346B2

    公开(公告)日：2022-11-01

    申请号：US16890819

    申请日：2020-06-02

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  Yantao Ma ,  Yasushi Matsubara ,  Takamasa Suzuki

    IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3234 ,  G11C11/22

    Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

    LEAKAGE CURRENT REDUCTION IN ELECTRONIC DEVICES
    5.
    发明申请
    LEAKAGE CURRENT REDUCTION IN ELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20200177184A1

    公开(公告)日：2020-06-04

    申请号：US16205953

    申请日：2018-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Hiroshi Akamatsu ,  Ki-Jun Nam ,  John David Porter

    IPC: H03K19/00 ,  H03K19/096

    Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

    APPARATUSES AND METHODS FOR CAPTURING DATA USING A DIVIDED CLOCK
    6.
    发明申请
    APPARATUSES AND METHODS FOR CAPTURING DATA USING A DIVIDED CLOCK 有权
    使用分开的时钟捕获数据的装置和方法

    公开(公告)号：US20160172018A1

    公开(公告)日：2016-06-16

    申请号：US14571735

    申请日：2014-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  John David Porter

    IPC: G11C7/22 ,  H03K21/00 ,  G11C7/10

    CPC classification number: G11C7/1012 ,  G11C7/00 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/18 ,  G11C2207/107 ,  H03K3/017 ,  H03K5/1502 ,  H03L7/06

    Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.

    Abstract translation: 描述了使用分时钟捕获数据的装置和方法。 示例性装置包括被配置为接收DQS信号并且提供分频时钟信号的时钟分配器。 分频时钟信号的分频时钟信号的频率小于DQS信号的频率。 该示例设备还包括命令电路，其被配置为接收命令，并且基于所划分的时钟信号以及从接收到该命令的时间开始确定的延迟来断言多个标志信号之一。 该示例设备还包括数据捕获电路，其配置为串行地接收与该命令相关联的数据，并且响应于划分的时钟信号提供反序列化数据。 数据捕获电路还被配置为基于所述多个标志信号中的所述一个标记信号对反序列化数据进行排序以提供分类数据。

    Apparatuses and methods for providing internal power voltages
    7.
    发明授权
    Apparatuses and methods for providing internal power voltages 有权

    公开(公告)号：US11914451B2

    公开(公告)日：2024-02-27

    申请号：US17893946

    申请日：2022-08-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ki-Jun Nam ,  Younghoon Oh

    IPC: G06F1/32 ,  G06F1/3296 ,  G11C11/4074

    CPC classification number: G06F1/3296 ,  G11C11/4074

    Abstract: Apparatuses and methods for providing internal power voltages are described. An example apparatus includes a first, second, and third clamp circuits, and a clamp control circuit. The first clamp circuit is configured to receive a first external power voltage and provide a first voltage drop to provide a first internal power voltage. The second clamp circuit is configured to receive the first external power voltage and provide a second voltage drop to provide a second internal power voltage, wherein the first voltage drop is greater than the second voltage drop. The third clamp circuit is configured to receive a second external power voltage and provide the second external power voltage as the second internal power voltage when the second external power voltage is activated. The clamp control circuit is configured to activate the third clamp circuit when the second external power voltage reaches a trigger voltage level.

    DC VOLTAGE REGULATORS WITH DEMAND-DRIVEN POWER MANAGEMENT
    9.
    发明申请
    DC VOLTAGE REGULATORS WITH DEMAND-DRIVEN POWER MANAGEMENT 有权

    公开(公告)号：US20220129028A1

    公开(公告)日：2022-04-28

    申请号：US17571170

    申请日：2022-01-07

    Applicant: Micron Technology, Inc.

    Inventor： Si Hong Kim ,  Ki-Jun Nam

    IPC: G05F1/613 ,  G11C11/4074 ,  H02M3/158 ,  G06F1/26 ,  G11C11/22

    Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.

    BOUNDARY PROTECTION IN MEMORY
    10.
    发明申请
    BOUNDARY PROTECTION IN MEMORY 有权

    公开(公告)号：US20220076725A1

    公开(公告)日：2022-03-10

    申请号：US17524514

    申请日：2021-11-11

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  Hiroshi Akamatsu ,  Takamasa Suzuki ,  Yasushi Matsubara

    IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/30

    Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

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