公开(公告)号：US20240346152A1

公开(公告)日：2024-10-17

申请号：US18135694

申请日：2023-04-17

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Mallik BULUSU ,  Muhammad A. AHMED ,  Ganesh KUMAR A ,  Kiran Bangalore SATHYANARAYANA ,  Pingfan SONG

IPC: G06F21/57 ,  G06F21/12

CPC classification number: G06F21/577 ,  G06F21/126

Abstract: Disclosed herein is a system for limiting the rate at which system management interrupts can suspend normal execution of a central processing unit (CPU) by switching the operating mode of the CPU from one of the real mode or the protected mode to the system management mode. The rate limits imposed by the system provides a protective layer against cyberattacks (e.g., a distributed denial-of-service (DDoS) attack) from malicious actors and ensures the CPU can be more efficient regarding the execution of workloads (e.g., processing threads).

公开(公告)号：US20220066766A1

公开(公告)日：2022-03-03

申请号：US17008310

申请日：2020-08-31

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ravi MYSORE SHANTAMURTHY ,  Muhammad Ashfaq AHMED ,  Mallik BULUSU ,  Neeraj LADKANI ,  Sagar DHARIA

IPC: G06F8/65 ,  G06F9/4401 ,  G06F16/903 ,  G06F9/455

Abstract: While booting a host computing device on a cloud computing system, system firmware (such as Basic Input/Output System (BIOS) or Unified Extensible Firmware Interface (UEFI)) sends a query to a management subsystem (such as a baseboard management controller (BMC)) for updated configuration data used during a boot of the host computing device. The management subsystem sends the updated configuration data to the system firmware, and boot instructions in the system firmware compare the updated configuration data with configuration data stored on the host computing device. If the respective configuration data match, the boot instructions continue with booting the host computing device. If the configuration data do not match, then the boot instructions update the stored configuration data with the updated configuration data and then proceed to boot the host computing device.

公开(公告)号：US20210240489A1

公开(公告)日：2021-08-05

申请号：US16874276

申请日：2020-05-14

Applicant: Microsoft Technology Licensing, LLC

Inventor： Daini XIE ,  Thirupathaiah ANNAPUREDDY ,  Mallik BULUSU ,  Muhammad Ashfaq AHMED

IPC: G06F9/4401 ,  G06F9/54 ,  G06F8/654 ,  G06F21/64 ,  G06F21/57

Abstract: A computing system is provided, including a processor and memory storing instructions that, when executed, cause the processor to store a firmware update patch in a runtime buffer included in the memory. The runtime buffer may be accessible by firmware and an operating system of the computing system. The processor may perform a first verification check on the firmware update patch. When the firmware update patch passes the first verification check, the processor may copy the firmware update patch to a system management random access memory (SMRAM) buffer included in the memory. The SMRAM buffer may be accessible by the firmware and inaccessible by the operating system. The processor may perform a second verification check on the copy of the firmware update patch. When the copy of the firmware update patch passes the second verification check, the processor may execute the copy of the firmware update patch.

公开(公告)号：US20230229423A1

公开(公告)日：2023-07-20

申请号：US18189791

申请日：2023-03-24

Applicant: Microsoft Technology Licensing, LLC

Inventor： Neeraj LADKANI ,  Daini XIE ,  Mallik BULUSU ,  Muhammad Ashfaq AHMED

IPC: G06F8/65 ,  G06F13/42

CPC classification number: G06F8/65 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0042

Abstract: A host computing device includes a host processor, host memory in electronic communication with the host processor, and an auxiliary service controller. The host computing device also includes a communication interface and a messaging interface between the host processor and the auxiliary service controller. A message handler is stored in the host memory. The message handler is executable by the host processor in response to detecting a messaging interface signal on the messaging interface. Execution of the message handler by the host processor causes a firmware update patch to be read from a shared memory region in the auxiliary service controller via the communication interface.

公开(公告)号：US20220318093A1

公开(公告)日：2022-10-06

申请号：US17221751

申请日：2021-04-02

Applicant: Microsoft Technology Licensing, LLC

Inventor： Mallik BULUSU ,  Muhammad Ashfaq AHMED ,  Tom Long NGUYEN ,  Neeraj LADKANI ,  Ravi MYSORE SHANTAMURTHY

IPC: G06F11/14 ,  G06F11/07

Abstract: To preserve error context during a reboot of a computing device, firmware within the computing device can be configured to implement a method that includes determining where the error context is stored in volatile memory. The method can also include identifying a plurality of recorder regions in non-volatile memory that have been assigned to store the error context. The plurality of recorder regions can be disaggregated across a plurality of distinct non-volatile memory regions. The method can also include flushing the error context from a plurality of different volatile memory locations to the plurality of recorder regions in response to detecting a trigger. The flushing can occur prior to the reboot of the computing device. The method can also include restoring at least some of the error context to the volatile memory after the computing device has been rebooted.

公开(公告)号：US20190179628A1

公开(公告)日：2019-06-13

申请号：US15838085

申请日：2017-12-11

Applicant: Microsoft Technology Licensing, LLC

Inventor： Mallik BULUSU ,  Ramakoti R. BHIMANADHUNI ,  Ravi MYSORE SHANTAMURTHY

IPC: G06F9/445 ,  G06F9/4401 ,  G06F21/57

Abstract: Example techniques for updating a firmware, such as BIOS, are disclosed. Upon receiving an update, it is determined whether a secondary non-volatile memory is defined for the firmware. If the secondary non-volatile memory is defined, the update may be written in the secondary non-volatile memory. Further, to apply the update, a warm reboot of the firmware may be performed. The warm reboot causes an OS of the computing system to restart, while preserving data associated with applications running on the computing system.

公开(公告)号：US20190163557A1

公开(公告)日：2019-05-30

申请号：US15828138

申请日：2017-11-30

Applicant: Microsoft Technology Licensing, LLC

Inventor： Tom L. NGUYEN ,  Mallik BULUSU

IPC: G06F11/07 ,  G06F11/10 ,  G11C29/04 ,  G11C29/52

Abstract: In some examples, error recovery in volatile memory regions may include determining, during a save operation that includes saving of data to a primary location, that an error occurred with respect to the save operation. Based on a determination that the error occurred with respect to the save operation, an error location may be determined, and a determination may be made as to whether the error location maps to a volatile memory region. Based on a determination that the error location maps to the volatile memory region, a reserved location may be identified for saving the data. The data may be saved from the primary location to the reserved location. Further, metadata may be updated to indicate usage of the reserved location as the primary location for the saved data.

公开(公告)号：US20180165101A1

公开(公告)日：2018-06-14

申请号：US15378406

申请日：2016-12-14

Applicant: Microsoft Technology Licensing, LLC

Inventor： Mallik BULUSU ,  Bryan KELLY ,  Tom Long NGUYEN

IPC: G06F9/44

Abstract: Technologies are described which permit kernel updates or firmware fixes, and include re-initialization of kernel data structures, without losing user context information that has been created by services, virtual machines, or user applications. Tailored code in a server or other computing system sets a kernel soft reset (KSR) indicator and saves the user context to non-volatile storage. When a KSR is underway, boot code skips the power on self-test and similar initializations (thereby reducing downtime), loads a kernel image, initializes kernel data structures, restores the user context, and passes control to the initialized kernel to continue computing system operation with the same user context. Device drivers may also be re-initialized. The loaded kernel may use newly fixed firmware, or may have a security patch installed, for instance. The non-volatile storage may operate at RAM speed, e.g., it may include NVDIMM memory. The kernel may be validated before receiving control.

公开(公告)号：US20240403149A1

公开(公告)日：2024-12-05

申请号：US18325830

申请日：2023-05-30

Applicant: Microsoft Technology Licensing, LLC

Inventor： Karunakara KOTARY ,  Mallik BULUSU ,  Michael Alan KUBACKI

IPC: G06F8/65 ,  G06F9/4401 ,  G06F9/54

Abstract: The described technology provides a method including reserving a portion of a volatile memory on a system on chip (SOC) including one or more processors, decompressing at least a portion of the firmware code from a non-volatile memory; programming one or more volatile memory access control registers to remove write access to the reserved portion of the volatile memory, programming a memory activation table (MAT), wherein the MAT includes a set of memory access controller register addresses and values of the memory access controller register addresses, and communicating an address of the reserved portion of the volatile memory and the MAT to a trusted execution engine (TEE) on the SOC.

公开(公告)号：US20240264941A1

公开(公告)日：2024-08-08

申请号：US18635949

申请日：2024-04-15

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ravi MYSORE SHANTAMURTHY ,  Mallik BULUSU ,  Tom Long NGUYEN ,  Muhammad Ashfaq AHMED ,  Madhav Himanshubhai PANDYA

IPC: G06F12/0804 ,  G06F11/16 ,  G06F11/20 ,  G06F13/40

CPC classification number: G06F12/0804 ,  G06F11/2053 ,  G06F13/4027 ,  G06F11/1612 ,  G06F2212/1032

Abstract: A computing system that enables data stored in a persistent memory region to be preserved when a processor fails can include volatile memory comprising the persistent memory region, non-volatile memory, and a system on a chip (SoC). The SoC can include a main processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include an auxiliary processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.