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    Architecture for 3-D NAND memory
    1.
    发明授权
    Architecture for 3-D NAND memory 有权
    3-D NAND存储器架构

    公开(公告)号：US08964474B2

    公开(公告)日：2015-02-24

    申请号：US13524872

    申请日：2012-06-15

    申请人： Midori Morooka ,  Tomoharu Tanaka

    发明人： Midori Morooka ,  Tomoharu Tanaka

    IPC分类号： G11C16/00

    CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/3427 ,  G11C2213/71

    摘要： Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

    摘要翻译： 描述了包括存储器单元串的堆叠阵列及其操作方法的装置。 装置包括减少几个常用部件的使用的结构，允许给定半导体区域的更大的器件密度和更小的器件尺寸。

    Non-volatile semiconductor memory device
    3.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07486559B2

    公开(公告)日：2009-02-03

    申请号：US11740493

    申请日：2007-04-26

    申请人： Midori Morooka ,  Koichi Fukuda

    发明人： Midori Morooka ,  Koichi Fukuda

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/20

    摘要： 2 or more sets of initial setup data specifying different operation conditions are stored in a memory cell array comprising electrically-rewritable non-volatile memory cells arranged therein. A control circuit reads a set of initial setup data out of the 2 or more sets of initial setup data via an sense amplifier circuit based on the area information. The initial setup data is transferred to an initial setup data latch and stored therein.

    摘要翻译： 指定不同操作条件的2组以上的初始设定数据被存储在包括布置在其中的电可重写非易失性存储单元的存储单元阵列中。 控制电路通过基于区域信息的读出放大器电路，从2组以上的初始设定数据中读出一组初始设定数据。 初始设置数据被传送到初始设置数据锁存器并存储在其中。

    Semiconductor memory device
    4.
    发明申请
    Semiconductor memory device 失效

    公开(公告)号：US20060245259A1

    公开(公告)日：2006-11-02

    申请号：US11412938

    申请日：2006-04-28

    申请人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

    发明人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

    IPC分类号： G11C11/34

    CPC分类号： G11C16/20 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

    摘要： A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

    Semiconductor integrated circuit device wherein during data write a potential transferred to each bit line is changed in accordance with program order of program data
    6.
    发明授权
    Semiconductor integrated circuit device wherein during data write a potential transferred to each bit line is changed in accordance with program order of program data 失效
    半导体集成电路器件，其中在数据写入期间，根据程序数据的程序顺序改变传送到每个位线的电位

    公开(公告)号：US07564713B2

    公开(公告)日：2009-07-21

    申请号：US11411940

    申请日：2006-04-27

    申请人： Midori Morooka

    发明人： Midori Morooka

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3404

    摘要： The present invention discloses a semiconductor integrated circuit device having nonvolatile semiconductor memory cells, bit lines each connected to one end of the nonvolatile semiconductor memory cells, and a data circuit connected to the bit lines to temporarily store program data for the nonvolatile semiconductor memory cells. During a data write operation, the data circuit changes a potential transferred to each bit line in accordance with a program order of the program data.

    摘要翻译： 本发明公开了一种具有非易失性半导体存储单元的半导体集成电路器件，各自连接到非易失性半导体存储单元的一端的位线以及连接到位线的数据电路，以临时存储用于非易失性半导体存储单元的程序数据。 在数据写入操作期间，数据电路根据程序数据的程序顺序改变传送到每个位线的电位。

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20080025101A1

    公开(公告)日：2008-01-31

    申请号：US11862552

    申请日：2007-09-27

    申请人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

    发明人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

    IPC分类号： G11C11/34

    CPC分类号： G11C16/20 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

    摘要： A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

    摘要翻译： 半导体存储器件包括：存储单元阵列; 用于逐页读取和写入存储单元阵列的数据的读出放大器电路; 验证判断电路，被配置为基于保持在读出放大器电路中的验证读取数据来判断写入或擦除完成; 以及为存储单元阵列中的各列设置的数据锁存器被附加到验证判断电路，校验判断电路被写入用于排除来自验证对象的相应列的列分离数据，其中列分离数据被自动设置 在初始设置模式下的数据锁存器处于上电时间，使得用户的至少一部分不可访问的列从验证对象中排除。

    Semiconductor integrated circuit device
    8.
    发明申请
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US20060245261A1

    公开(公告)日：2006-11-02

    申请号：US11411940

    申请日：2006-04-27

    申请人： Midori Morooka

    发明人： Midori Morooka

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3404

    摘要： The present invention discloses a semiconductor integrated circuit device having nonvolatile semiconductor memory cells, bit lines each connected to one end of the nonvolatile semiconductor memory cells, and a data circuit connected to the bit lines to temporarily store program data for the nonvolatile semiconductor memory cells. During a data write operation, the data circuit changes a potential transferred to each bit line in accordance with a program order of the program data.

    摘要翻译： 本发明公开了一种具有非易失性半导体存储单元的半导体集成电路器件，各自连接到非易失性半导体存储单元的一端的位线以及连接到位线的数据电路，以临时存储用于非易失性半导体存储单元的程序数据。 在数据写入操作期间，数据电路根据程序数据的程序顺序改变传送到每个位线的电位。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07515473B2

    公开(公告)日：2009-04-07

    申请号：US11862552

    申请日：2007-09-27

    申请人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

    发明人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

    IPC分类号： G11C16/06

    CPC分类号： G11C16/20 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

    摘要： A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

    摘要翻译： 半导体存储器件包括：存储单元阵列; 用于逐页读取和写入存储单元阵列的数据的读出放大器电路; 验证判断电路，被配置为基于保持在读出放大器电路中的验证读取数据来判断写入或擦除完成; 以及为存储单元阵列中的各列设置的数据锁存器被附加到验证判断电路，校验判断电路被写入用于排除来自验证对象的相应列的列分离数据，其中列分离数据被自动设置 在初始设置模式下的数据锁存器处于上电时间，使得用户的至少一部分不可访问的列从验证对象中排除。