公开(公告)号：US20080025101A1

公开(公告)日：2008-01-31

申请号：US11862552

申请日：2007-09-27

申请人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

发明人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

IPC分类号： G11C11/34

CPC分类号： G11C16/20 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

摘要： A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

摘要翻译： 半导体存储器件包括：存储单元阵列; 用于逐页读取和写入存储单元阵列的数据的读出放大器电路; 验证判断电路，被配置为基于保持在读出放大器电路中的验证读取数据来判断写入或擦除完成; 以及为存储单元阵列中的各列设置的数据锁存器被附加到验证判断电路，校验判断电路被写入用于排除来自验证对象的相应列的列分离数据，其中列分离数据被自动设置 在初始设置模式下的数据锁存器处于上电时间，使得用户的至少一部分不可访问的列从验证对象中排除。

公开(公告)号：US07515473B2

公开(公告)日：2009-04-07

申请号：US11862552

申请日：2007-09-27

申请人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

发明人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

IPC分类号： G11C16/06

CPC分类号： G11C16/20 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

摘要： A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

摘要翻译： 半导体存储器件包括：存储单元阵列; 用于逐页读取和写入存储单元阵列的数据的读出放大器电路; 验证判断电路，被配置为基于保持在读出放大器电路中的验证读取数据来判断写入或擦除完成; 以及为存储单元阵列中的各列设置的数据锁存器被附加到验证判断电路，校验判断电路被写入用于排除来自验证对象的相应列的列分离数据，其中列分离数据被自动设置 在初始设置模式下的数据锁存器处于上电时间，使得用户的至少一部分不可访问的列从验证对象中排除。

公开(公告)号：US07277325B2

公开(公告)日：2007-10-02

申请号：US11412938

申请日：2006-04-28

申请人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

发明人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

IPC分类号： G11C16/06

CPC分类号： G11C16/20 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

摘要： A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

摘要翻译： 半导体存储器件包括：存储单元阵列; 用于逐页读取和写入存储单元阵列的数据的读出放大器电路; 验证判断电路，被配置为基于保持在读出放大器电路中的验证读取数据来判断写入或擦除完成; 以及为存储单元阵列中的各列设置的数据锁存器被附加到验证判断电路，校验判断电路被写入用于排除来自验证对象的相应列的列分离数据，其中列分离数据被自动设置 在初始设置模式下的数据锁存器处于上电时间，使得用户的至少一部分不可访问的列从验证对象中排除。

公开(公告)号：US07486559B2

公开(公告)日：2009-02-03

申请号：US11740493

申请日：2007-04-26

申请人： Midori Morooka ,  Koichi Fukuda

发明人： Midori Morooka ,  Koichi Fukuda

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/20

摘要： 2 or more sets of initial setup data specifying different operation conditions are stored in a memory cell array comprising electrically-rewritable non-volatile memory cells arranged therein. A control circuit reads a set of initial setup data out of the 2 or more sets of initial setup data via an sense amplifier circuit based on the area information. The initial setup data is transferred to an initial setup data latch and stored therein.

摘要翻译： 指定不同操作条件的2组以上的初始设定数据被存储在包括布置在其中的电可重写非易失性存储单元的存储单元阵列中。 控制电路通过基于区域信息的读出放大器电路，从2组以上的初始设定数据中读出一组初始设定数据。 初始设置数据被传送到初始设置数据锁存器并存储在其中。

公开(公告)号：US20060245259A1

公开(公告)日：2006-11-02

申请号：US11412938

申请日：2006-04-28

申请人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

发明人： Koichi Fukuda ,  Midori Morooka ,  Hiroyuki Dohmae

IPC分类号： G11C11/34

CPC分类号： G11C16/20 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

摘要： A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

公开(公告)号：US09165964B2

公开(公告)日：2015-10-20

申请号：US13817387

申请日：2011-08-12

申请人： Koichi Fukuda

发明人： Koichi Fukuda

IPC分类号： H01L27/146 ,  G03B13/36 ,  H04N5/225

CPC分类号： H01L27/14627 ,  G03B13/36 ,  H01L27/14605 ,  H01L27/1461 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H04N5/2256 ,  H04N5/23212 ,  H04N5/3696

摘要： An image sensor in which each pixel includes a first sub-pixel including a first semiconductor layer, a second sub-pixel including a second semiconductor layer having a polarity different from a polarity of the first semiconductor layer, a third semiconductor layer having a polarity equal to the polarity of the first semiconductor layer, and a microlens, and which includes a plurality of pixels in which the first semiconductor is included in the second semiconductor layer, and the second semiconductor layer is included in the third semiconductor layer, wherein a center of gravity position of a light-receiving surface defining the first semiconductor layer is different from a center of gravity position of a light-receiving surface defining both the first semiconductor layer and the second semiconductor layer.

摘要翻译： 一种图像传感器，其中每个像素包括包括第一半导体层的第一子像素，包括具有与第一半导体层的极性不同的极性的第二半导体层的第二子像素，具有极性相等的第三半导体层 涉及第一半导体层的极性和微透镜，并且其包括多个像素，其中第一半导体包括在第二半导体层中，并且第二半导体层包括在第三半导体层中，其中， 限定第一半导体层的光接收表面的重力位置不同于限定第一半导体层和第二半导体层的光接收表面的重心位置。

公开(公告)号：US09025060B2

公开(公告)日：2015-05-05

申请号：US13428515

申请日：2012-03-23

申请人： Akihiro Nishio ,  Ichiro Onuki ,  Koichi Fukuda ,  Ryo Yamasaki ,  Hideaki Yamamoto ,  Makoto Oikawa

发明人： Akihiro Nishio ,  Ichiro Onuki ,  Koichi Fukuda ,  Ryo Yamasaki ,  Hideaki Yamamoto ,  Makoto Oikawa

IPC分类号： H04N3/14 ,  H04N3/12 ,  H04N5/225 ,  H04N5/232 ,  H04N5/238 ,  H04N1/46 ,  G02F1/1335 ,  H01L27/146 ,  H01L31/062 ,  H01L31/0203 ,  H04N5/369

CPC分类号： H04N5/3696 ,  G03B13/36 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H04N5/23212

摘要： A solid-state image sensor which comprises a pixel group in which unit pixels each including a microlens and a plurality of photo-electric converters are arrayed two-dimensionally, wherein a shielding unit that shields part of all of a plurality of photo-electric converters corresponding to a single microlens is provided in a portion of the unit pixels.

摘要翻译： 一种固态图像传感器，其包括像素组，其中包括微透镜和多个光电转换器的单位像素二维排列，其中屏蔽单元屏蔽所有多个光电转换器 对应于单个微透镜的单位像素的一部分。

公开(公告)号：US09003105B2

公开(公告)日：2015-04-07

申请号：US13603697

申请日：2012-09-05

申请人： Ayako Yamano ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

发明人： Ayako Yamano ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

IPC分类号： G06F12/08 ,  G06F12/02 ,  G11C16/00 ,  G11C11/56 ,  G11C16/16

CPC分类号： G06F12/0891 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/16 ,  Y02D10/13

摘要： According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管 每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到 具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定 当第一个标志表示有效时，块是可写的。

公开(公告)号：US08836010B2

公开(公告)日：2014-09-16

申请号：US13344765

申请日：2012-01-06

申请人： Koichi Fukuda ,  Rieko Tanaka ,  Takumi Abe

发明人： Koichi Fukuda ,  Rieko Tanaka ,  Takumi Abe

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/105 ,  H01L49/02

CPC分类号： H01L27/11531 ,  H01L27/105 ,  H01L27/11526 ,  H01L28/24

摘要： A nonvolatile semiconductor memory device including a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

摘要翻译： 一种非易失性半导体存储器件，包括被配置为存储数据的存储单元和设置在存储单元周围的电阻元件。 存储单元包括设置在基板上的电荷存储层，经由绝缘层形成在电荷存储层的顶表面上的第一半导体层和形成在第一半导体层的顶表面上的第一低电阻层，并且具有 电阻低于第一半导体层的电阻。 电阻元件包括形成在与第一半导体层相同的层上的第二半导体层，以及形成在与第一低电阻层相同的层上的第二低电阻层，以及形成在第二半导体层的顶表面上的第二低电阻层， 比第二半导体层的厚度大。

公开(公告)号：US08791517B2

公开(公告)日：2014-07-29

申请号：US13052152

申请日：2011-03-21

申请人： Hiroyuki Kutsukake ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

发明人： Hiroyuki Kutsukake ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

IPC分类号： H01L29/78 ,  H01L29/92

CPC分类号： H01L27/11526 ,  H01L27/11521 ,  H01L27/11529

摘要： According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

摘要翻译： 根据一个实施例，半导体器件包括设置在半导体衬底中的至少一个半导体区域和包括设置在半导体区域中的多个电容器的电容器组，每个电容器包括设置在半导体区域上的电容器绝缘膜，电容器 设置在电容器绝缘膜上的电极以及设置在与电容器电极相邻的半导体区域中的至少一个扩散层。