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    Semiconductor integrated circuit having a built-in data storage circuit for nonvolatile storage of control data
    1.
    发明授权
    Semiconductor integrated circuit having a built-in data storage circuit for nonvolatile storage of control data 失效
    具有用于非易失存储控制数据的内置数据存储电路的半导体集成电路

    公开(公告)号：US06577551B2

    公开(公告)日：2003-06-10

    申请号：US10007148

    申请日：2001-12-04

    申请人： Mikihiko Ito ,  Masaru Koyanagi ,  Takahiko Hara ,  Satoru Takase ,  Tohru Kimura

    发明人： Mikihiko Ito ,  Masaru Koyanagi ,  Takahiko Hara ,  Satoru Takase ,  Tohru Kimura

    IPC分类号： G11C700

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit (6) is divided into groups (1, 2), and the read control circuit (7) generates read control signals for the groups (1, 2) at different timings, using an output of an internal potential detecting circuit 41 as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.

    摘要翻译： 半导体集成电路包括具有编程控制数据的非易失性存储装置的控制数据存储电路（6）和用于保存从存储装置读出的数据的锁存电路，以及用于控制控制的读取操作的读取控制电路（7） 数据，内置在半导体芯片中。 控制数据存储电路（6）被分成组（1,2），读取控制电路（7）使用内部电位检测的输出在不同的定时产生用于组（1,2）的读取控制信号 电路41作为定时参考，从而防止功耗峰值在读取操作期间不可接受地上升。

    Dynamic random access memory device and semiconductor integrated circuit device
    2.
    发明授权
    Dynamic random access memory device and semiconductor integrated circuit device 有权
    动态随机存取存储器件和半导体集成电路器件

    公开(公告)号：US06496442B2

    公开(公告)日：2002-12-17

    申请号：US10076558

    申请日：2002-02-19

    申请人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

    发明人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

    IPC分类号： G11C800

    CPC分类号： G11C8/18 ,  G11C8/12 ,  G11C11/406

    摘要： A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

    摘要翻译： 包括多个具有多个子阵列的多个存储体的DRAM和通常由不同存储体中的子阵列共享的读出放大器电路具有用于激活从每个存储体中选择的用于读取或写入的子阵列的行访问模式 数据和刷新模式，用于激活每个存储体中的多个子阵列，并以基本相同的定时刷新存储器单元数据。 在刷新模式中基本上相同的定时激活的每个存储体中的子阵列多于在行存取模型中激活的每个存储体中的子阵列。 由此，操作约束的发生被最小化以确保高速操作，并且提高采用非独立银行系统的DRAM的系统性能。

    Semiconductor storage device
    6.
    发明授权
    Semiconductor storage device 失效
    半导体存储设备

    公开(公告)号：US07027335B2

    公开(公告)日：2006-04-11

    申请号：US10720980

    申请日：2003-11-24

    申请人： Mikihiko Ito ,  Masaru Koyanagi ,  Takashi Taira

    发明人： Mikihiko Ito ,  Masaru Koyanagi ,  Takashi Taira

    IPC分类号： G11C7/00

    CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065 ,  G11C2207/2281

    摘要： A semiconductor storage device comprises a memory cell array including memory cells, and bit lines for transfer of data in the memory cells; an amplifier circuit connected to the bit lines to amplify data in the memory cells; a first switching element connected between the bit lines and the amplifier circuit; a first reference voltage source which applies to the gate of the first switching element a voltage for turning the first switching element ON; a second switching element and a third switching element connected in series between the gate of the first switching element and the first reference voltage source, said second switching element and said third switching element being connected in parallel to each other; a second reference voltage source which applies to the gates of the second and third switching elements a voltage for turning the second and third switching elements ON; and a first timing shift circuit connected between the gate of the third switching element and the second reference voltage source to delay the operation of the third switching element from the operation of the second switching element.

    摘要翻译： 半导体存储装置包括存储单元阵列，其包括存储单元，以及用于在存储单元中传送数据的位线; 连接到位线的放大器电路，以放大存储器单元中的数据; 连接在位线与放大电路之间的第一开关元件; 第一参考电压源，其向第一开关元件的栅极施加用于使第一开关元件导通的电压; 第二开关元件和第三开关元件串联连接在第一开关元件的栅极和第一参考电压源之间，所述第二开关元件和所述第三开关元件彼此并联连接; 第二参考电压源，其向第二和第三开关元件的栅极施加用于使第二和第三开关元件接通的电压; 以及连接在第三开关元件的栅极和第二参考电压源之间的第一定时偏移电路，用于延迟第三开关元件的操作与第二开关元件的操作。

    Dynamic type semiconductor memory apparatus
    7.
    发明申请
    Dynamic type semiconductor memory apparatus 失效
    动态型半导体存储装置

    公开(公告)号：US20050213395A1

    公开(公告)日：2005-09-29

    申请号：US11079369

    申请日：2005-03-15

    申请人： Mikihiko Ito ,  Masaru Koyanagi

    发明人： Mikihiko Ito ,  Masaru Koyanagi

    IPC分类号： G11C11/409 ,  G11C5/00 ,  G11C11/401

    CPC分类号： G11C7/1018 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4045 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4097

    摘要： A dynamic type semiconductor memory apparatus performs an operation of continuous column access at a high speed while minimizing an increase of a chip size. The dynamic type semiconductor memory apparatus includes first and second memory cell groups divided based on a column address, a first bit line connected to the first memory cell group, a second bit line connected to the second memory cell group, first and second local data lines, and a column selection unit configured to connect the first and second bit lines to the first and second local data line based on a column address. The dynamic type semiconductor memory apparatus further includes first and second master data line, a local data line selecting unit configured to connect the first and second local data lines to the first and second master data lines, respectively, a DBR configured to read data from the first or second master data lines, and a DWB configured to write data to the first or second master data lines.

    摘要翻译： 动态类型半导体存储装置在最大限度地提高芯片尺寸的同时，高速地执行连续的列存取操作。 动态型半导体存储装置包括基于列地址划分的第一和第二存储单元组，连接到第一存储单元组的第一位线，连接到第二存储单元组的第二位线，第一和第二本地数据线 以及列选择单元，被配置为基于列地址将第一和第二位线连接到第一和第二本地数据线。 动态型半导体存储装置还包括第一和第二主数据线，本地数据线选择单元，被配置为分别将第一和第二本地数据线连接到第一和第二主数据线，DBR被配置为从 第一或第二主数据线，以及被配置为将数据写入到第一或第二主数据线的DWB。

    Dynamic type semiconductor memory apparatus
    8.
    发明授权
    Dynamic type semiconductor memory apparatus 失效
    动态型半导体存储装置

    公开(公告)号：US07133303B2

    公开(公告)日：2006-11-07

    申请号：US11079369

    申请日：2005-03-15

    申请人： Mikihiko Ito ,  Masaru Koyanagi

    发明人： Mikihiko Ito ,  Masaru Koyanagi

    IPC分类号： G11C5/06

    CPC分类号： G11C7/1018 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4045 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4097

    摘要： A dynamic type semiconductor memory apparatus performs an operation of continuous column access at a high speed while minimizing an increase of a chip size. The dynamic type semiconductor memory apparatus includes first and second memory cell groups divided based on a column address, a first bit line connected to the first memory cell group, a second bit line connected to the second memory cell group, first and second local data lines, and a column selection unit configured to connect the first and second bit lines to the first and second local data line based on a column address. The dynamic type semiconductor memory apparatus further includes first and second master data line, a local data line selecting unit configured to connect the first and second local data lines to the first and second master data lines, respectively, a DBR configured to read data from the first or second master data lines, and a DWB configured to write data to the first or second master data lines.

    摘要翻译： 动态型半导体存储装置在最大限度地提高芯片尺寸的同时，高速地进行连续的列存取操作。 动态型半导体存储装置包括基于列地址划分的第一和第二存储单元组，连接到第一存储单元组的第一位线，连接到第二存储单元组的第二位线，第一和第二本地数据线 以及列选择单元，被配置为基于列地址将第一和第二位线连接到第一和第二本地数据线。 动态型半导体存储装置还包括第一和第二主数据线，本地数据线选择单元，被配置为分别将第一和第二本地数据线连接到第一和第二主数据线，DBR被配置为从 第一或第二主数据线，以及被配置为将数据写入到第一或第二主数据线的DWB。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06498741B2

    公开(公告)日：2002-12-24

    申请号：US09746890

    申请日：2000-12-21

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    IPC分类号： G11C506

    CPC分类号： G11C5/063

    摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

    摘要翻译： 提供一种半导体存储器件，其确保存储器数据传输时间和高速操作的对称性，并且具有大的写入/读取操作裕度，而不需要增加芯片面积。 通过在半导体芯片的垂直方向上的中间放置一个水平长的外围电路部分，将垂直长的移位寄存器部分设置在周边电路部分的上下方向并垂直于外围电路部分，并使存储器核心和移位寄存器装置在 水平方向，可以使存储器芯和移位寄存器部分之间的数据/信号线短，并且可以保持互连的对称性，这允许实现高速和大面积的半导体存储器件。 另外，通过将每个对应于数据块的移位寄存器堆叠并选择堆叠移位寄存器的顺序，使得外围电路与移位之间的互连长度可以获得更快的半导体存储器 寄存器被最小化。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06198649B1

    公开(公告)日：2001-03-06

    申请号：US09460641

    申请日：1999-12-15

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    IPC分类号： G11C506

    CPC分类号： G11C5/063

    摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.