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    Three-dimensional package and method of making the same
    1.
    发明申请
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US20070172985A1

    公开(公告)日：2007-07-26

    申请号：US11645042

    申请日：2006-12-26

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chain-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chain-Chi Lin

    IPC分类号： H01L21/00

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/00012

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a metal; (g) removing the dry film, and patterning the conductive layer; (h) removing a part of the metal in the blind hole to form a space; (i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal; (k) stacking a plurality of the wafers, and performing a reflow process; and (l) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供晶片; （b）在所述晶片中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）在导电层上形成干膜; （f）用金属填充盲孔; （g）去除干膜，图案化导电层; （h）去除盲孔中的金属的一部分以形成空间; （i）去除所述晶片的所述第二表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （j）在导电层的下端形成焊料，其中焊料的熔点低于金属的熔点; （k）堆叠多个晶片，并进行回流处理; 和（l）切割堆叠的晶片，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到下晶片的空间中，以增强导电层和焊料之间的接合，并且有效地降低了三层结构的整体高度， 加入后立体包装。

    Three-dimensional package and method of making the same
    3.
    发明授权
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US07642132B2

    公开(公告)日：2010-01-05

    申请号：US11584546

    申请日：2006-10-23

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/44

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少 加入后三维包装的整体高度。

    Three-dimensional package and method of making the same
    6.
    发明申请
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US20070172986A1

    公开(公告)日：2007-07-26

    申请号：US11645177

    申请日：2006-12-26

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/00

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/00012

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package structure comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal, a first solder, a second wafer, at least one second hole, a second isolation layer, a second conductive layer, a second metal and a second space. The first wafer has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The lower end of the first conductive layer extends below the surface of the first wafer. The first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. The second wafer has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole. The lower end of the second conductive layer extends below the surface of the second wafer and contacts the upper end of the first solder. The second metal is disposed in the second hole and is electrically connected to the second pad via the second conductive layer. The second space is disposed on the second metal in the second hole.

    摘要翻译： 本发明涉及三维包装及其制造方法。 三维封装结构包括第一晶片，至少一个第一孔，第一隔离层，第一导电层，第一金属，第一焊料，第二晶片，至少一个第二孔，第二隔离层， 第二导电层，第二金属和第二空间。 第一晶片具有至少一个第一焊盘和暴露第一焊盘的第一保护层。 第一个孔穿透第一个晶片。 第一隔离层设置在第一孔的侧壁上。 第一导电层的下端延伸到第一晶片的表面下方。 第一金属设置在第一孔中，并且经由第一导电层电连接到第一焊盘。 第一焊料设置在第一孔中的第一金属上，其中第一焊料的熔点低于第一焊料的熔点。 第二晶片具有至少一个第二焊盘和暴露第二焊盘的第二保护层。 第二孔穿透第二晶片。 第二隔离层设置在第二孔的侧壁上。 第二导电层的下端延伸到第二晶片的表面下方并接触第一焊料的上端。 第二金属设置在第二孔中，并通过第二导电层与第二焊盘电连接。 第二空间设置在第二孔中的第二金属上。

    Three-dimensional package and method of making the same
    7.
    发明授权
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US07741152B2

    公开(公告)日：2010-06-22

    申请号：US11645040

    申请日：2006-12-26

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 一种制造三维封装的方法，包括：（a）提供晶片; （b）形成至少一个盲孔; （c）形成隔离层; （d）形成导电层; （e）形成干膜; （f）用焊料填充盲孔; （g）去除干膜; （h）图案化导电层; （i）去除晶片的下表面的一部分和隔离层，以暴露导电层; （j）堆叠多个晶片，并进行回流处理; 和（k）切割堆叠的晶片，以便形成多个三维封装。 因此，导电层的下端插入下晶片的焊料中，以增强导电层和焊料之间的接合，并且有效地降低了连接后三维封装的整体高度。

    Three-dimensional package and method of making the same
    8.
    发明申请
    Three-dimensional package and method of making the same 审中-公开
    三维包装及其制作方法

    公开(公告)号：US20070172983A1

    公开(公告)日：2007-07-26

    申请号：US11645039

    申请日：2006-12-26

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first solder, a second wafer, at least one second hole, a second isolation layer, a second conductive layer, and a second solder. The first wafer has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The lower end of the first conductive layer extends below the surface of the first wafer. The first solder is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The second wafer has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole. The lower end of the second conductive layer extends to below the surface of the second wafer and contacts the upper end of the first solder. The second solder is disposed in the second hole and is electrically connected to the second pad via the second conductive layer.

    摘要翻译： 本发明涉及三维包装及其制造方法。 三维封装包括第一晶片，至少一个第一孔，第一隔离层，第一导电层，第一焊料，第二晶片，至少一个第二孔，第二隔离层，第二导电层， 和第二焊料。 第一晶片具有至少一个第一焊盘和暴露第一焊盘的第一保护层。 第一个孔穿透第一个晶片。 第一隔离层设置在第一孔的侧壁上。 第一导电层的下端延伸到第一晶片的表面下方。 第一焊料设置在第一孔中，并且经由第一导电层电连接到第一焊盘。 第二晶片具有至少一个第二焊盘和暴露第二焊盘的第二保护层。 第二孔穿透第二晶片。 第二隔离层设置在第二孔的侧壁上。 第二导电层的下端延伸到第二晶片的表面下方并接触第一焊料的上端。 第二焊料设置在第二孔中，并通过第二导电层与第二焊盘电连接。

    Three-dimensional package and method of making the same
    10.
    发明申请
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US20070172984A1

    公开(公告)日：2007-07-26

    申请号：US11645040

    申请日：2006-12-26

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供晶片; （b）在所述晶片中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）在导电层上形成干膜; （f）用焊料填充盲孔; （g）去除干膜; （h）图案化导电层; （i）去除所述晶片的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （j）堆叠多个晶片，并进行回流处理; 和（k）切割堆叠的晶片，以便形成多个三维封装。 因此，导电层的下端插入下晶片的焊料中，以增强导电层和焊料之间的接合，并且有效地降低了连接后三维封装的整体高度。