公开(公告)号：US20060163569A1

公开(公告)日：2006-07-27

申请号：US11218397

申请日：2005-09-02

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： H01L22/34

摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

公开(公告)号：US07317204B2

公开(公告)日：2008-01-08

申请号：US11218397

申请日：2005-09-02

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

IPC分类号： H01L23/58

CPC分类号： H01L22/34

摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

公开(公告)号：US20060113534A1

公开(公告)日：2006-06-01

申请号：US11243595

申请日：2005-10-05

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  H01L22/34

摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

公开(公告)号：US07501651B2

公开(公告)日：2009-03-10

申请号：US11243595

申请日：2005-10-05

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  H01L22/34

摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

摘要翻译： 提供了具有改善的测试可靠性的半导体器件的测试结构。 测试结构包括彼此电隔离并且分别在其上形成有硅化的第一和第二结区的第一和第二有源区，形成在第一和第二结区的下部的半导体衬底或阱，以及 具有不同于第一和第二接合区域的导电类型，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到第一和第二接合区域并被检测，并且形成在与金属的下部相同的高度上 层或与半导体衬底相同的水平。

公开(公告)号：US06797559B2

公开(公告)日：2004-09-28

申请号：US10283844

申请日：2002-10-30

申请人： Chang-won Lee ,  Si-young Choi ,  Seong-jun Heo ,  Sung-man Kim ,  Min-chul Sun ,  Ja-hum Ku ,  Sun-pil Youn

发明人： Chang-won Lee ,  Si-young Choi ,  Seong-jun Heo ,  Sung-man Kim ,  Min-chul Sun ,  Ja-hum Ku ,  Sun-pil Youn

IPC分类号： H01L218242

CPC分类号： H01L29/6656 ,  H01L21/28044 ,  H01L29/4941

摘要： A method of manufacturing a semiconductor device having a metal conducting layer is provided. A metal conducting layer pattern having the metal conducting layer is formed on a semiconductor substrate. A portion of the metal conducting layer is partially exposed on the semiconductor substrate. The semiconductor substrate having the metal conducting layer pattern is loaded into a reaction chamber. A first silicon source gas is flowed into the reaction chamber. A silicon oxide layer is formed on the semiconductor substrate having the metal conducting layer pattern by supplying a second silicon source gas and an oxygen source gas into the reaction chamber.

摘要翻译： 提供一种制造具有金属导电层的半导体器件的方法。 具有金属导电层的金属导电层图案形成在半导体衬底上。 金属导电层的一部分部分露出在半导体衬底上。 具有金属导电层图案的半导体衬底被加载到反应室中。 第一硅源气体流入反应室。 通过向反应室供给第二硅源气体和氧源气体，在具有金属导电层图案的半导体衬底上形成氧化硅层。

公开(公告)号：US20070298600A1

公开(公告)日：2007-12-27

申请号：US11425841

申请日：2006-06-22

申请人： Bong-seok Suh ,  Hong-jae Shin ,  Sun-jung Lee ,  Min-chul Sun ,  Jung-hoon Lee

发明人： Bong-seok Suh ,  Hong-jae Shin ,  Sun-jung Lee ,  Min-chul Sun ,  Jung-hoon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/76846

摘要： A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming a nickel silicide layer on surfaces of the gate electrodes and the source/drain regions by evaporating nickel or nickel alloy on the semiconductor substrate formed with the gate electrodes and the source/drain regions and then performing a thermal process on the nickel or the nickel alloy; forming an interlayer insulating layer, which is formed with contact holes through which a surface of the nickel silicide layer is exposed, on a surface obtained after the above processes have been performed; forming an ohmic layer by evaporating a refractory metal conformably along the contact holes, the refractory metal being converted to silicide at a temperature of 500° C. or more; forming a diffusion barrier on the ohmic layer conformably along the contact holes; and forming a metal layer by burying a metal material within the contact holes.

摘要翻译： 一种制造半导体器件的方法及其制造的半导体器件。 制造半导体器件的方法包括在半导体衬底上形成栅电极; 在半导体衬底内形成源/漏区，以便位于每个栅电极的两侧; 通过在形成有栅电极和源极/漏极区域的半导体衬底上蒸发镍或镍合金，然后在镍或镍上进行热处理，在栅电极和源/漏区的表面上形成硅化镍层 合金; 形成层间绝缘层，所述层间绝缘层在进行上述处理后得到的表面上形成有暴露所述镍硅化物层的表面的接触孔; 通过沿着接触孔顺应蒸发难熔金属形成欧姆层，难熔金属在500℃或更高的温度下转化为硅化物; 在欧姆层上沿着接触孔顺应地形成扩散阻挡层; 以及通过在接触孔内埋入金属材料来形成金属层。