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    Test structure of semiconductor device
    2.
    发明授权
    Test structure of semiconductor device 有权
    半导体器件的测试结构

    公开(公告)号：US07501651B2

    公开(公告)日：2009-03-10

    申请号：US11243595

    申请日：2005-10-05

    申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

    发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

    IPC分类号： H01L23/58

    CPC分类号： G01R31/2884 ,  H01L22/34

    摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

    摘要翻译： 提供了具有改善的测试可靠性的半导体器件的测试结构。 测试结构包括彼此电隔离并且分别在其上形成有硅化的第一和第二结区的第一和第二有源区，形成在第一和第二结区的下部的半导体衬底或阱，以及 具有不同于第一和第二接合区域的导电类型，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到第一和第二接合区域并被检测，并且形成在与金属的下部相同的高度上 层或与半导体衬底相同的水平。

    Test structure of semiconductor device
    3.
    发明申请
    Test structure of semiconductor device 有权
    半导体器件的测试结构

    公开(公告)号：US20060163569A1

    公开(公告)日：2006-07-27

    申请号：US11218397

    申请日：2005-09-02

    申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

    发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

    IPC分类号： H01L23/58 ,  H01L29/10

    CPC分类号： H01L22/34

    摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

    摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

    Test structure of semiconductor device
    4.
    发明授权
    Test structure of semiconductor device 有权
    半导体器件的测试结构

    公开(公告)号：US07317204B2

    公开(公告)日：2008-01-08

    申请号：US11218397

    申请日：2005-09-02

    申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

    发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

    IPC分类号： H01L23/58

    CPC分类号： H01L22/34

    摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

    摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

    Embedded stressor structure and process
    6.
    发明申请
    Embedded stressor structure and process 有权
    嵌入式应力器结构与过程

    公开(公告)号：US20070132038A1

    公开(公告)日：2007-06-14

    申请号：US11297522

    申请日：2005-12-08

    申请人： Yung Chong ,  Zhijiong Luo ,  Joo Kim ,  Brian Greene ,  Kern Rim

    发明人： Yung Chong ,  Zhijiong Luo ,  Joo Kim ,  Brian Greene ,  Kern Rim

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.

    摘要翻译： 示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫 门。 包括以下的示例性方法。 我们在衬底的第一区域上提供栅极结构。 栅极结构由栅极电介质，栅极和侧壁间隔物组成。 我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。 我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。 形成填充S / D凹槽的S / D应力区域。 与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

    Enhancing MOSFET performance with corner stresses of STI
    7.
    发明授权
    Enhancing MOSFET performance with corner stresses of STI 有权
    通过STI拐角应力增强MOSFET性能

    公开(公告)号：US09356025B2

    公开(公告)日：2016-05-31

    申请号：US14348579

    申请日：2012-03-29

    申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

    发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

    IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

    CPC分类号： H01L27/092 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66575 ,  H01L29/7846

    摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.

    摘要翻译： 本发明涉及利用STI的拐角应力来增强MOSFET的性能。 一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光​​区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准 地区。

    SEMICONDUCTOR PLATE DEVICE
    8.
    发明申请
    SEMICONDUCTOR PLATE DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150171272A1

    公开(公告)日：2015-06-18

    申请号：US14567720

    申请日：2014-12-11

    申请人： Zhijiong Luo

    发明人： Zhijiong Luo

    IPC分类号： H01L33/20 ,  H01L31/18 ,  H01L33/00 ,  H01L31/0352

    CPC分类号： H01L33/20 ,  H01L31/022425 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/042 ,  H01L31/0504 ,  H01L31/0684 ,  H01L31/077 ,  H01L31/1804 ,  H01L31/1876 ,  Y02E10/547 ,  Y02P70/521

    摘要： Technologies are generally described for providing solar device or LED device structures and methods for manufacturing the same, which may allow for making ultra-thin semiconductor plate devices with flexible contact arrangements at the meantime of maintaining or improving performance of solar devices, improving the utility of the semiconductor plate material, and increasing the fabrication through-put and yield of the solar and LED devices.

    摘要翻译： 技术通常被描述为提供太阳能装置或LED装置结构及其制造方法，其可以允许制造具有柔性接触装置的超薄半导体板装置，同时保持或改善太阳能装置的性能，从而提高太阳能装置的效用 半导体板材料，并且增加了太阳能和LED器件的制造通过量和产量。

    Semiconductor device with a common back gate isolation region and method for manufacturing the same
    9.
    发明授权
    Semiconductor device with a common back gate isolation region and method for manufacturing the same 有权
    具有公共背栅隔离区的半导体器件及其制造方法

    公开(公告)号：US09054221B2

    公开(公告)日：2015-06-09

    申请号：US13510807

    申请日：2011-11-18

    申请人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

    发明人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.

    摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每一个均形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中相应的相邻MOSFET在半导体内部和相应的后栅极直接接触并与之直接接触。 衬底，并且PNP结或NPN结由公共背栅隔离区和相应的相邻MOSFET的相应背栅形成。 根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。 此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。 结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

    Non-volatile memory device using finfet and method for manufacturing the same
    10.
    发明授权
    Non-volatile memory device using finfet and method for manufacturing the same 有权
    使用finfet的非易失性存储器件及其制造方法

    公开(公告)号：US08981454B2

    公开(公告)日：2015-03-17

    申请号：US13061461

    申请日：2010-09-25

    申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

    发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

    IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

    摘要： The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.

    摘要翻译： 本申请公开了一种非易失性存储器件，其包括绝缘层上的半导体鳍片; 在半导体鳍片的中心部分处的沟道区域; 半导体鳍片两侧的源极/漏极区域; 布置在半导体鳍片的第一侧并沿远离半导体鳍片的方向延伸的浮动栅极; 以及布置在所述浮动栅极的顶部上或覆盖所述浮动栅极的顶部和侧壁部分的第一控制栅极。 非易失性存储器件减少短通道效应，具有增加的存储器密度，并且是成本有效的。