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    Test structure of semiconductor device
    1.
    发明申请
    Test structure of semiconductor device 有权
    半导体器件的测试结构

    公开(公告)号：US20060163569A1

    公开(公告)日：2006-07-27

    申请号：US11218397

    申请日：2005-09-02

    申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

    发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

    IPC分类号： H01L23/58 ,  H01L29/10

    CPC分类号： H01L22/34

    摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

    摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

    Test structure of semiconductor device
    2.
    发明授权
    Test structure of semiconductor device 有权
    半导体器件的测试结构

    公开(公告)号：US07317204B2

    公开(公告)日：2008-01-08

    申请号：US11218397

    申请日：2005-09-02

    申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

    发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

    IPC分类号： H01L23/58

    CPC分类号： H01L22/34

    摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

    摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

    Test structure of semiconductor device
    4.
    发明授权
    Test structure of semiconductor device 有权
    半导体器件的测试结构

    公开(公告)号：US07501651B2

    公开(公告)日：2009-03-10

    申请号：US11243595

    申请日：2005-10-05

    申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

    发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

    IPC分类号： H01L23/58

    CPC分类号： G01R31/2884 ,  H01L22/34

    摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

    摘要翻译： 提供了具有改善的测试可靠性的半导体器件的测试结构。 测试结构包括彼此电隔离并且分别在其上形成有硅化的第一和第二结区的第一和第二有源区，形成在第一和第二结区的下部的半导体衬底或阱，以及 具有不同于第一和第二接合区域的导电类型，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到第一和第二接合区域并被检测，并且形成在与金属的下部相同的高度上 层或与半导体衬底相同的水平。

    Semiconductor devices with rotated substrates and methods of manufacture thereof
    5.
    发明申请
    Semiconductor devices with rotated substrates and methods of manufacture thereof 有权
    具有旋转基板的半导体器件及其制造方法

    公开(公告)号：US20060202277A1

    公开(公告)日：2006-09-14

    申请号：US11076080

    申请日：2005-03-09

    申请人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

    发明人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/78

    摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

    摘要翻译： 集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向在0至45度之间旋转的角度定向在基板上。 诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。 对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

    Methods of manufacturing semiconductor devices with rotated substrates
    6.
    发明申请
    Methods of manufacturing semiconductor devices with rotated substrates 有权
    制造具有旋转衬底的半导体器件的方法

    公开(公告)号：US20070173003A1

    公开(公告)日：2007-07-26

    申请号：US11710382

    申请日：2007-02-23

    申请人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

    发明人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

    IPC分类号： H01L21/337

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/78

    摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

    摘要翻译： 集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向旋转5至40度的角度定向在基板上。 诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。 对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

    Methods of Forming Conductive Features and Structures Thereof
    8.
    发明申请
    Methods of Forming Conductive Features and Structures Thereof 审中-公开
    形成导电特性及结构的方法

    公开(公告)号：US20110175148A1

    公开(公告)日：2011-07-21

    申请号：US13074888

    申请日：2011-03-29

    申请人： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    发明人： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    IPC分类号： H01L29/772

    CPC分类号： H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

    摘要翻译： 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

    Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups
    9.
    发明申请
    Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups 有权
    相同基板设备组中的阈值电压一致性和有效宽度

    公开(公告)号：US20090227086A1

    公开(公告)日：2009-09-10

    申请号：US12043384

    申请日：2008-03-06

    申请人： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

    发明人： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76262 ,  H01L21/76278

    摘要： The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

    摘要翻译： 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。