公开(公告)号：US20060163569A1

公开(公告)日：2006-07-27

申请号：US11218397

申请日：2005-09-02

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： H01L22/34

摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

公开(公告)号：US20060113534A1

公开(公告)日：2006-06-01

申请号：US11243595

申请日：2005-10-05

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  H01L22/34

摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

公开(公告)号：US20070249131A1

公开(公告)日：2007-10-25

申请号：US11408522

申请日：2006-04-21

申请人： Scott Allen ,  Cyril Cabral ,  Kevin Dezfulian ,  Sunfei Fang ,  Brian Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement Wann ,  Huilong Zhu

发明人： Scott Allen ,  Cyril Cabral ,  Kevin Dezfulian ,  Sunfei Fang ,  Brian Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement Wann ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/268 ,  H01L21/2686 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/324 ,  H01L29/517 ,  H01L29/665

摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

公开(公告)号：US20070132038A1

公开(公告)日：2007-06-14

申请号：US11297522

申请日：2005-12-08

申请人： Yung Chong ,  Zhijiong Luo ,  Joo Kim ,  Brian Greene ,  Kern Rim

发明人： Yung Chong ,  Zhijiong Luo ,  Joo Kim ,  Brian Greene ,  Kern Rim

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.

摘要翻译： 示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫 门。 包括以下的示例性方法。 我们在衬底的第一区域上提供栅极结构。 栅极结构由栅极电介质，栅极和侧壁间隔物组成。 我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。 我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。 形成填充S / D凹槽的S / D应力区域。 与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

公开(公告)号：US20060202277A1

公开(公告)日：2006-09-14

申请号：US11076080

申请日：2005-03-09

申请人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

发明人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

IPC分类号： H01L29/94

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/78

摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

摘要翻译： 集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向在0至45度之间旋转的角度定向在基板上。 诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。 对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

公开(公告)号：US20070173003A1

公开(公告)日：2007-07-26

申请号：US11710382

申请日：2007-02-23

申请人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

发明人： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

IPC分类号： H01L21/337

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/78

摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

摘要翻译： 集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向旋转5至40度的角度定向在基板上。 诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。 对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

公开(公告)号：US07657582B1

公开(公告)日：2010-02-02

申请号：US11197694

申请日：2005-08-04

申请人： Paul Cram ,  Stephen Andrew Breidbach ,  Anthony T. Orling ,  Brian Greene

发明人： Paul Cram ,  Stephen Andrew Breidbach ,  Anthony T. Orling ,  Brian Greene

IPC分类号： G06F12/00

CPC分类号： G06F11/1435 ,  G06F11/1451 ,  G06F11/1453 ,  G06F11/1458 ,  G06F11/1469 ,  G06F11/2071 ,  G06F11/2079 ,  G06F2201/84

摘要： A system for using recent activity information to select backup versions of storage objects for restoration comprises a processor and memory coupled to the processor, where the memory stores program instructions computer-executable by the processor to implement a backup manager. The backup manager is configured to maintain one or more backup versions of a plurality of storage objects and a plurality of access history records, where each access history record is associated with a particular backup version. Each access history record includes information indicative of an access to the corresponding storage object by a user. The backup manager may be configured to select a particular backup version as a restoration candidate using at least the contents of the access history record associated with the backup version.

摘要翻译： 用于使用最近的活动信息来选择用于恢复的存储对象的备份版本的系统包括耦合到处理器的处理器和存储器，其中存储器存储由处理器计算机可执行以执行备份管理器的程序指令。 备份管理器被配置为维护多个存储对象和多个访问历史记录的一个或多个备份版本，其中每个访问历史记录与特定备份版本相关联。 每个访问历史记录包括指示用户访问对应的存储对象的信息。 备份管理器可以被配置为使用至少与备份版本相关联的访问历史记录的内容来选择特定备份版本作为恢复候选。

公开(公告)号：US20070164358A1

公开(公告)日：2007-07-19

申请号：US11333074

申请日：2006-01-17

申请人： Joel de Souza ,  Keith Fogel ,  Brian Greene ,  Devendra Sadana ,  Haining Yang

发明人： Joel de Souza ,  Keith Fogel ,  Brian Greene ,  Devendra Sadana ,  Haining Yang

IPC分类号： H01L27/12 ,  H01L29/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US20070096223A1

公开(公告)日：2007-05-03

申请号：US11163686

申请日：2005-10-27

申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

IPC分类号： H01L27/12

CPC分类号： H01L29/1083 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/31675 ,  H01L29/7833 ,  H01L29/7846

摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below a second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, the edges extending in directions away from the upper surface.

摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 具有水平延伸的上表面的第一介电应激元件在有源半导体区域的一部分的下方延伸，例如有源半导体区域的西北部分。 具有水平延伸的上表面的第二介电应激元件在有源半导体区域的第二部分的下方延伸，例如有源半导体区域的东南部分。 第一和第二介电应力元件中的每一个与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。

公开(公告)号：US20070093036A1

公开(公告)日：2007-04-26

申请号：US11259297

申请日：2005-10-26

申请人： Kangguo Cheng ,  Brian Greene ,  Jack Mandelman

发明人： Kangguo Cheng ,  Brian Greene ,  Jack Mandelman

IPC分类号： H01L21/30 ,  H01L21/20 ,  H01L21/76

CPC分类号： H01L21/76251 ,  H01L21/76245 ,  Y10S438/933

摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.

摘要翻译： 一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。 在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。 多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。 或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。 在转移之后，绝缘层被埋在后面的衬底和含锗层之间。