公开(公告)号：US20120319201A1

公开(公告)日：2012-12-20

申请号：US13412760

申请日：2012-03-06

申请人： Min-Chul Sun ,  Byung-Gook Park

发明人： Min-Chul Sun ,  Byung-Gook Park

IPC分类号： H01L27/092

CPC分类号： H01L27/1104 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/7827

摘要： In a semiconductor device, a vertical transistor comprises: a first diffusion region on a substrate; a channel region on the first diffusion region and extending in a vertical direction; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.

摘要翻译： 在半导体器件中，垂直晶体管包括：衬底上的第一扩散区; 在所述第一扩散区域上的沿垂直方向延伸的沟道区域; 沟道区上的第二扩散区; 以及在沟道区的侧壁处和绝缘的栅电极。 水平晶体管位于衬底上，水平晶体管包括：在衬底上的第一扩散区和第二扩散区，彼此间隔开; 在所述第一扩散区域和所述第二扩散区域之间的衬底上的沟道区域; 以及沟道区上的栅极，并与沟道区分离。 垂直晶体管的栅电极的一部分和水平晶体管的栅电极的一部分在垂直方向上相对于衬底处于相同的垂直位置。

公开(公告)号：US20120164807A1

公开(公告)日：2012-06-28

申请号：US13408311

申请日：2012-02-29

申请人： Min-Chul SUN ,  Dong-Suk Shin ,  Jung-Deog Lee

发明人： Min-Chul SUN ,  Dong-Suk Shin ,  Jung-Deog Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/088 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6656

摘要： A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region.

摘要翻译： 一种半导体器件及其制造方法，半导体器件包括半导体衬底，半导体衬底上的栅极绝缘层，具有侧壁的栅电极，栅极绝缘层，栅电极的侧壁上的第一间隔物， 源极/漏极区域，与侧壁对准，栅极上的硅化物层，源极/漏极区域上的硅化物层，以及覆盖第一间隔物和硅化物层的表面的端部的第二间隔物， 源极漏极区域。

公开(公告)号：US20080237586A1

公开(公告)日：2008-10-02

申请号：US11694449

申请日：2007-03-30

申请人： Min Chul Sun ,  Scott Jansen ,  Randy Mann ,  Oliver D. Patterson

发明人： Min Chul Sun ,  Scott Jansen ,  Randy Mann ,  Oliver D. Patterson

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L22/32

摘要： Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

摘要翻译： 半导体集成测试结构被设计用于半导体晶片的电子束检查。 测试结构包括与晶片上形成的集成电路的图形特征同时形成在晶片的指定测试区域中的图案特征。 测试结构包括导电结构，其被设计成能够在缺陷和非缺陷特征（或给定特征的有缺陷和非缺陷部分）之间进行差分充电，以便于CMOS器件的电压对比度缺陷检测，例如使用单个， 尽管晶片衬底或其他元件/特征中存在p / n结，但是低能电子束扫描也是如此。

公开(公告)号：US20060163569A1

公开(公告)日：2006-07-27

申请号：US11218397

申请日：2005-09-02

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Wee Tan ,  Sunfei Fang ,  Zhijiong Luo

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： H01L22/34

摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

公开(公告)号：US20060113534A1

公开(公告)日：2006-06-01

申请号：US11243595

申请日：2005-10-05

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian Greene ,  Manfred Eller ,  Roman Knoefler ,  Zhijiong Luo

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  H01L22/34

摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

公开(公告)号：US08928080B2

公开(公告)日：2015-01-06

申请号：US13554066

申请日：2012-07-20

申请人： Min-Chul Sun ,  Byung-Gook Park

发明人： Min-Chul Sun ,  Byung-Gook Park

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78648 ,  H01L29/78696

摘要： A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body.

摘要翻译： 背面偏置区域设置在基板上。 掩埋绝缘层覆盖基板和背偏置区域。 在掩埋绝缘层上形成一体并且部分地与背偏置区重叠。 排水管与身体接触。 栅电极覆盖身体的顶表面和侧表面。

公开(公告)号：US08557691B2

公开(公告)日：2013-10-15

申请号：US13550814

申请日：2012-07-17

申请人： Min-Chul Sun ,  Byung-Gook Park

发明人： Min-Chul Sun ,  Byung-Gook Park

IPC分类号： H01L21/425

CPC分类号： H01L21/76889 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2409 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.

摘要翻译： 根据发明构思的示例性实施例，制造半导体器件的方法包括在晶体硅衬底上形成具有SiGe的牺牲图案。 在牺牲图案上形成具有晶体硅的主体。 在身体上形成至少一个活动元件。 形成绝缘层以覆盖牺牲图案，主体和有源元件。 形成接触孔以通过绝缘层露出牺牲图案。 通过去除牺牲图案形成空隙。 在接触孔和空隙空间中形成非晶硅层。 将非晶硅层转变成金属硅化物层。

公开(公告)号：US08481392B1

公开(公告)日：2013-07-09

申请号：US13542717

申请日：2012-07-06

申请人： Min-Chul Sun ,  Byung-Gook Park

发明人： Min-Chul Sun ,  Byung-Gook Park

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.

摘要翻译： 制造半导体器件的方法及相关器件包括在衬底上形成栅电极，在栅电极的侧表面和栅电极附近形成第一缓冲层，第二缓冲层和第三缓冲层 形成覆盖第三缓冲层上的栅电极的侧表面的间隔物，衬底上的第三缓冲层被暴露，通过去除暴露的第三缓冲层而将第二缓冲层暴露在衬底上，将第一缓冲层暴露在 通过去除暴露的第二缓冲层，在衬底中使用间隔物作为掩模形成深结，并且去除衬垫。 第三缓冲层是具有比第二缓冲层更高的介电常数的材料层。 间隔物包括与第三，第二和第一缓冲层不同的材料层。

公开(公告)号：US20130171810A1

公开(公告)日：2013-07-04

申请号：US13542717

申请日：2012-07-06

申请人： Min-Chul Sun ,  Byung-Gook Park

发明人： Min-Chul Sun ,  Byung-Gook Park

IPC分类号： H01L21/425

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.

摘要翻译： 制造半导体器件的方法及相关器件包括在衬底上形成栅电极，在栅电极的侧表面和栅电极附近形成第一缓冲层，第二缓冲层和第三缓冲层 形成覆盖第三缓冲层上的栅电极的侧表面的间隔物，衬底上的第三缓冲层被暴露，通过去除暴露的第三缓冲层而将第二缓冲层暴露在衬底上，将第一缓冲层暴露在 通过去除暴露的第二缓冲层，在衬底中使用间隔物作为掩模形成深结，并且去除衬垫。 第三缓冲层是具有比第二缓冲层更高的介电常数的材料层。 间隔物包括与第三，第二和第一缓冲层不同的材料层。

公开(公告)号：US20080217612A1

公开(公告)日：2008-09-11

申请号：US11683058

申请日：2007-03-07

申请人： Oliver D. Patterson ,  Horatio Seymour Wildman ,  Min-Chul Sun

发明人： Oliver D. Patterson ,  Horatio Seymour Wildman ,  Min-Chul Sun

IPC分类号： H01L23/58

CPC分类号： H01L22/34

摘要： Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.

摘要翻译： 本发明的实施例提供了用于集成电路检查的测试结构。 测试结构可以与一个或多个集成电路一起制造在半导体晶片上。 测试结构可以包括用于参考电压的公共参考点; 多个降压装置连接到公共参考点; 并且多个电子收集垫分别连接到多个降压装置的多个接触点。 在集成电路的检查期间由多个电子收集板所示的亮度可以与预定电压相关联。