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    DECISION FEEDBACK EQUALIZER SUMMATION CIRCUIT
    1.
    发明申请
    DECISION FEEDBACK EQUALIZER SUMMATION CIRCUIT 审中-公开
    决策反馈均衡器建立电路

    公开(公告)号：US20160087817A1

    公开(公告)日：2016-03-24

    申请号：US14492237

    申请日：2014-09-22

    申请人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

    发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

    IPC分类号： H04L25/03 ,  H04L25/06 ,  H04L25/08

    CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

    摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

    摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

    DECISION FEEDBACK EQUALIZER
    2.
    发明申请
    DECISION FEEDBACK EQUALIZER 有权
    决策反馈均衡器

    公开(公告)号：US20130346811A1

    公开(公告)日：2013-12-26

    申请号：US13528877

    申请日：2012-06-21

    申请人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

    发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

    IPC分类号： G06F1/04 ,  G06F11/00

    CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

    摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

    摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

    PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS
    3.
    发明申请
    PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS 有权
    用于具有主动波形整合器的时钟数据恢复电路的相位插值器

    公开(公告)号：US20140037035A1

    公开(公告)日：2014-02-06

    申请号：US13564758

    申请日：2012-08-02

    申请人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

    发明人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

    IPC分类号： H03D3/24

    CPC分类号： H03K5/135 ,  H03H11/20 ,  H03K2005/00052 ,  H04L7/0029

    摘要： A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

    摘要翻译： 用于CDR电路的相位插值器产生具有在两个输入时钟上的电平转换之间的电平转换的输出时钟。 输入时钟驱动交叉耦合差分放大器，输出可根据输入控制值通过可变电流节流或转向相位变化。 差分放大器产生一个输出信号，该输出信号跨越在引导输入时钟之间的转换开始到延迟输入时钟转换结束之间的时间。 输出时钟是线性的，只要两个输入时钟的转换重叠即可。 每个具有串联电阻和电容反馈路径的放大器的积分器耦合到交叉耦合差分放大器的每个输入，这增强了输入时钟上升时间的重叠，并提高了内插输出信号的线性度。

    DECISION FEEDBACK EQUALIZER HAVING PROGRAMMABLE TAPS
    4.
    发明申请
    DECISION FEEDBACK EQUALIZER HAVING PROGRAMMABLE TAPS 有权
    具有可编程功能的决策反馈均衡器

    公开(公告)号：US20130121396A1

    公开(公告)日：2013-05-16

    申请号：US13293513

    申请日：2011-11-10

    申请人： Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

    发明人： Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

    IPC分类号： H04L27/01

    CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

    摘要： A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

    摘要翻译： 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

    PHASE LOCKED LOOP CALIBRATION
    5.
    发明申请
    PHASE LOCKED LOOP CALIBRATION 有权
    相位锁定校准

    公开(公告)号：US20130082754A1

    公开(公告)日：2013-04-04

    申请号：US13252498

    申请日：2011-10-04

    申请人： Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

    发明人： Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

    IPC分类号： H03L7/08

    CPC分类号： H03L7/102 ,  H03L7/099 ,  H03L2207/06

    摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

    摘要翻译： 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

    METHOD AND APPARATUS FOR FEEDBACK-BASED RESISTANCE CALIBRATION
    6.
    发明申请
    METHOD AND APPARATUS FOR FEEDBACK-BASED RESISTANCE CALIBRATION 有权
    基于反馈电阻校准的方法和装置

    公开(公告)号：US20140015611A1

    公开(公告)日：2014-01-16

    申请号：US13547101

    申请日：2012-07-12

    申请人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

    发明人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

    IPC分类号： H03F3/04

    CPC分类号： G01R31/2621

    摘要： A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

    摘要翻译： 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

    DRIVERS HAVING T-COIL STRUCTURES
    7.
    发明申请
    DRIVERS HAVING T-COIL STRUCTURES 有权
    具有T型线圈结构的驱动器

    公开(公告)号：US20130099767A1

    公开(公告)日：2013-04-25

    申请号：US13278742

    申请日：2011-10-21

    申请人： Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Yuwen SWEI ,  Chiang PU

    发明人： Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Yuwen SWEI ,  Chiang PU

    IPC分类号： G05F3/02

    CPC分类号： H03H11/44 ,  H01S5/0427 ,  H04B10/504

    摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

    摘要翻译： 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。

    CAPACTIVE LOAD PLL WITH CALIBRATION LOOP
    9.
    发明申请
    CAPACTIVE LOAD PLL WITH CALIBRATION LOOP 有权
    具有校准环路的电容负载PLL

    公开(公告)号：US20130342247A1

    公开(公告)日：2013-12-26

    申请号：US13530136

    申请日：2012-06-22

    申请人： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

    发明人： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

    IPC分类号： H03L7/08

    CPC分类号： H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

    摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

    摘要翻译： 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。