公开(公告)号：US08488362B2

公开(公告)日：2013-07-16

申请号：US12431983

申请日：2009-04-29

申请人： Ming-Daou Lee ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

发明人： Ming-Daou Lee ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

IPC分类号： G11C11/00

CPC分类号： H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/112

摘要： Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

摘要翻译： 描述存储器件以及用于制造的方法和操作方法。 如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。 多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在 对应的字线和相应的位线。 该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

公开(公告)号：US20100277967A1

公开(公告)日：2010-11-04

申请号：US12431983

申请日：2009-04-29

申请人： MING-DAOU LEE ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

发明人： MING-DAOU LEE ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien-Hung Yeh

IPC分类号： G11C11/00 ,  H01L47/00

CPC分类号： H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/112

摘要： Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

摘要翻译： 描述存储器件以及用于制造的方法和操作方法。 如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。 多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在 对应的字线和相应的位线。 该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

公开(公告)号：US20120108031A1

公开(公告)日：2012-05-03

申请号：US13346935

申请日：2012-01-10

申请人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/02

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US08114715B2

公开(公告)日：2012-02-14

申请号：US12654810

申请日：2010-01-05

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/82

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US20090072211A1

公开(公告)日：2009-03-19

申请号：US11898529

申请日：2007-09-13

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US08927956B2

公开(公告)日：2015-01-06

申请号：US12403186

申请日：2009-03-12

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L45/00 ,  G11C11/00 ,  G11C13/00 ,  G11C11/54 ,  G11C11/14 ,  G11C11/56

CPC分类号： G11C11/54 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10S438/972

摘要： A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

摘要翻译： 提供电阻型存储器件。 电阻型存储器件包括第一和第二导体和金属氧化物层。 金属氧化物层设置在第一和第二导体之间，电阻型存储装置被定义为第一电阻率。 在向金属氧化物层施加第一脉冲电压之后，将电阻型存储器件定义为第二电阻率。 在向金属氧化物层施加第二脉冲电压之后，将电阻型存储器件定义为第三电阻率。 第二电阻率大于第一电阻率，第一电阻率大于第三电阻率。

公开(公告)号：US07524722B2

公开(公告)日：2009-04-28

申请号：US11695780

申请日：2007-04-03

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： G11C11/54 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10S438/972

摘要： A resistance type memory device is provided. The resistance type memory device is disposed on a substrate and includes a tungsten electrode, an upper electrode, and a tungsten oxide layer. The upper electrode is disposed on the tungsten electrode. The tungsten oxide layer is sandwiched between the tungsten electrode and the upper electrode.

摘要翻译： 提供电阻型存储器件。 电阻型存储装置设置在基板上，并且包括钨电极，上电极和氧化钨层。 上电极设置在钨电极上。 氧化钨层夹在钨电极和上电极之间。

公开(公告)号：US20100112810A1

公开(公告)日：2010-05-06

申请号：US12654810

申请日：2010-01-05

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/28

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

公开(公告)号：US20090166604A1

公开(公告)日：2009-07-02

申请号：US12403186

申请日：2009-03-12

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L27/24

CPC分类号： G11C11/54 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10S438/972

摘要： A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

摘要翻译： 提供电阻型存储器件。 电阻型存储器件包括第一和第二导体和金属氧化物层。 金属氧化物层设置在第一和第二导体之间，电阻型存储装置被定义为第一电阻率。 在向金属氧化物层施加第一脉冲电压之后，将电阻型存储器件定义为第二电阻率。 在向金属氧化物层施加第二脉冲电压之后，将电阻型存储器件定义为第三电阻率。 第二电阻率大于第一电阻率，第一电阻率大于第三电阻率。

公开(公告)号：US20080237798A1

公开(公告)日：2008-10-02

申请号：US11867000

申请日：2007-10-04

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

摘要： A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.

摘要翻译： 提供了一种存储单元及其制造方法。 在该工艺中，在衬底上的导电层上形成第一电极层，然后在第一电极层上形成过渡金属层。 之后，对过渡金属层进行等离子体氧化工序，形成作为数据存储层的前体的过渡金属氧化物层，在过渡金属氧化物层上形成第二电极层。 在第二电极层，过渡金属氧化物层和第一电极层分别形成第二电极，数据存储层和第一电极之后形成存储单元。