公开(公告)号：US5904528A

公开(公告)日：1999-05-18

申请号：US785213

申请日：1997-01-17

申请人： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

发明人： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L21/823814 ,  H01L29/7835

摘要： Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

公开(公告)号：US6140186A

公开(公告)日：2000-10-31

申请号：US196439

申请日：1998-11-20

申请人： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

发明人： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L21/823814 ,  H01L29/7835

摘要： Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

摘要翻译： 晶体管的不对称掺杂的源极/漏极区域使用保护绝缘层形成，以防止栅电极的一部分接收到过多的杂质注入剂量，并穿过下面的栅极绝缘层进入半导体衬底。 在重植入期间采用侧壁间隔物。

公开(公告)号：US06667227B1

公开(公告)日：2003-12-23

申请号：US09574695

申请日：2000-05-17

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L214763

CPC分类号： H01L29/78 ,  H01L29/4933 ,  H01L29/66621

摘要： A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

摘要翻译： 金属氧化物半导体（MOS）晶体管和用于改进器件缩放的方法包括形成在半导体衬底内蚀刻的沟槽内的沟槽多晶硅栅极，并且还包括源极区域，漏极区域和沟道区域。 源极和漏极区域被形成沟槽的多晶硅栅极的沟槽横向分开，并且部分地在沟槽的底表面下方延伸。 沟槽区域形成在沟槽底面下方的硅衬底中。 在一个实施例中，沟槽多晶硅栅极的顶表面基本上平行于衬底表面。 在另一个实施例中，沟槽多晶硅栅极的顶表面和一部分设置在衬底表面上方。

公开(公告)号：US06285054B1

公开(公告)日：2001-09-04

申请号：US09052057

申请日：1998-03-30

申请人： Yowjuang W. Liu ,  Donald L. Wollesen

发明人： Yowjuang W. Liu ,  Donald L. Wollesen

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7883

摘要： A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench. The sidewall dopings are immediately contiguous the vertical sides of the trench and laterally separate the trench from the source region and the drain region.

摘要翻译： 用于非易失性半导体器件的器件结构和方法包括沟槽浮置栅极和控制栅极，并且还包括源极区域，漏极区域，沟道区域和栅极间电介质层。 沟槽浮栅形成在蚀刻到半导体衬底中的沟槽中。 沟槽浮动栅极具有与衬底的顶表面基本平坦的顶表面。 源极和漏极的深度大约等于或大于沟槽的深度，并且部分地在沟槽的底部下方延伸。 栅极间电介质层形成在沟槽浮置栅极的顶表面上，并且控制栅极形成在栅极间电介质层上。 在一个实施例中，器件结构还包括侧壁掺杂，其是形成在半导体衬底中的注入区域，其沿沟槽的长度基本上垂直延伸。 侧壁掺杂物紧邻于沟槽的垂直侧面并且横向地将沟槽与源区域和漏极区域分开。

公开(公告)号：US06201761B1

公开(公告)日：2001-03-13

申请号：US09491823

申请日：2000-01-26

申请人： Donald L. Wollesen

发明人： Donald L. Wollesen

IPC分类号： G11C702

CPC分类号： H01L27/1203 ,  G11C5/146

摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. A clock signal defines a clock period with an active portion and a wait portion. The source region and/or the drain region are coupled to a body pumping signal. The body pumping signal includes a negative voltage pulse occurring during the wait portion which sets the voltage of a body region of the FET to a preset voltage during such negative voltage pulse. Decay of the preset voltage is predictable such that operation of the FET can be controlled during the active portion.

摘要翻译： 在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。 时钟信号定义具有有效部分和等待部分的时钟周期。 源极区域和/或漏极区域耦合到主体泵浦信号。 身体泵送信号包括在等待部分期间发生的负电压脉冲，其在该负电压脉冲期间将FET的体区域的电压设置为预设电压。 预设电压的衰减是可预测的，使得可以在有源部分期间控制FET的操作。

公开(公告)号：US6124608A

公开(公告)日：2000-09-26

申请号：US992961

申请日：1997-12-18

申请人： Yowjuang William Liu ,  Yu Sun ,  Donald L. Wollesen

发明人： Yowjuang William Liu ,  Yu Sun ,  Donald L. Wollesen

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A non-volatile memory device having a trench structure and a shallow drain region is formed in a substrate, thereby facilitating increased densification, improved planarization and low power programming and erasing. Embodiments include forming first and second trenches in a substrate and, in each trench, sequentially forming a substantially U-shaped tunnel dielectric layer and a substantially U-shaped floating gate electrode. A dielectric layer is then formed on the floating gate electrode extending on the substrate surface and a substantially T-shaped control gate electrode is formed filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form a shallow drain region between the first and second trenches and source regions extending to a greater depth than the drain region. During ion implantation, a region containing an impurity of the first conductivity type is formed at the intersection of each trench and the substrate surface to prevent shorting between the source/drain region and gate electrodes.

摘要翻译： 在衬底中形成具有沟槽结构和浅漏区的非易失性存储器件，从而有助于增加致密化，改进的平面化和低功率编程和擦除。 实施例包括在衬底中形成第一和第二沟槽，并且在每个沟槽中顺序地形成基本上U形的隧道介电层和基本上U形的浮置栅电极。 然后在衬底表面上延伸的浮栅上形成电介质层，并且形成填充沟槽并在衬底上延伸的大致T形的控制栅电极。 侧壁间隔件形成在控制栅电极和电介质层的侧表面上，然后进行离子注入，以在第一和第二沟槽之间形成浅漏极区域，并且源极区域延伸到比漏极区域更深的深度。 在离子注入期间，在每个沟槽和衬底表面的交叉处形成含有第一导电类型的杂质的区域，以防止源极/漏极区域和栅电极之间的短路。

公开(公告)号：US5982691A

公开(公告)日：1999-11-09

申请号：US164412

申请日：1998-09-30

申请人： Sunil Narayan Shabde ,  Donald L. Wollesen

发明人： Sunil Narayan Shabde ,  Donald L. Wollesen

IPC分类号： G11C29/02 ,  G11C29/50 ,  G11C11/40

CPC分类号： G11C29/028 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401 ,  G11C11/41 ,  G11C2029/5002 ,  G11C2029/5006

摘要： Apparatus and methods for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes by measuring the charge Q.sub.c that flow through a node of an equivalent diode structure when the diode structure is impinged by a light pulse with energy equivalent to that of the alpha-particle and/or cosmic ray strikes. In one embodiment, the method includes the steps of producing a light pulse having a light pulse energy, the light pulse energy is at a first light pulse energy; applying the light pulse to the device at a predetermined location, the predetermined location having an area and a geometry; varying the light pulse energy to a second light pulse energy which generates a soft error; detecting soft errors in the device; providing a diode having the same area and geometry as the predetermined location; applying the light pulse with the second light pulse energy to the diode; and determining the amount of charges that flow through the diode. The present invention additionally provides inexpensive methods and apparatus that would accurately simulate an alpha-particle and/or cosmic ray strike in a predetermined area of a memory cell and for comparing different technologies and SRAM/DRAM designs by comparing this pulse energy needed to produce the soft error.

摘要翻译： 用于通过测量当二极管结构被光脉冲冲击时通过等效二极管结构的节点流过的电荷Qc来确定器件对由α粒子和/或宇宙射线产生的软误差的鲁棒性的装置和方法， 能量相当于α粒子和/或宇宙射线的能量。 在一个实施例中，该方法包括产生具有光脉冲能量的光脉冲的步骤，光脉冲能量处于第一光脉冲能量; 在预定位置将光脉冲施加到所述装置，所述预定位置具有区域和几何形状; 将光脉冲能量改变为产生软误差的第二光脉冲能量; 检测设备中的软错误; 提供具有与所述预定位置相同的面积和几何形状的二极管; 将具有第二光脉冲能量的光脉冲施加到二极管; 并确定流过二极管的电荷量。 本发明另外提供了廉价的方法和设备，其可以精确地模拟存储器单元的预定区域中的α粒子和/或宇宙射线的冲击，并且通过比较不同的技术和SRAM / DRAM设计来比较产生 软错误。

公开(公告)号：US5960271A

公开(公告)日：1999-09-28

申请号：US42786

申请日：1998-03-17

申请人： Donald L. Wollesen ,  Homi Fatemi

发明人： Donald L. Wollesen ,  Homi Fatemi

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L29/66621 ,  H01L29/456 ,  H01L29/49

摘要： A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

摘要翻译： 在半导体衬底中形成具有V形壁的沟槽或沟槽栅极的场效应晶体管，并且在V形壁上生长栅极氧化物到衬底表面，并且填充有诸如多晶硅的栅电极材料。 优选地，在填充沟槽之前，V形壁的底部是圆形的。 源极/漏极杂质可以扩散或注入到V形栅极的表面氧化物两侧的衬底区域中。 触点在场隔离中被制成源极，漏极和栅极，以完成结构。 所得到的FET结构包括具有常规源极和漏极的自对准V形栅极，该源极和漏极被场隔离包围，但具有小于栅极表面宽度的约一半的有效沟道长度（Leff）。 优选地，V形门的会聚壁在圆形凹入的底部中。 由于栅极的V形结构，所以施加漏极电压的沟道的有效饱和长度仅从源极的边缘延伸到半导体衬底内部的V形结构的尖端之前。 V形结构的漏极侧由于施加的漏极电压而变为耗尽区。 由于这种结构的这种特性，栅极的表面宽度可以是例如期望沟道长度的两倍或更多倍的距离，从而允许常规光刻用于限定比光刻极限短的栅极长度 。

公开(公告)号：US5689139A

公开(公告)日：1997-11-18

申请号：US526189

申请日：1995-09-11

申请人： Nguyen Duc Bui ,  Donald L. Wollesen

发明人： Nguyen Duc Bui ,  Donald L. Wollesen

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/12 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

CPC分类号： H01L23/528 ,  H01L23/53209 ,  H01L2924/0002

摘要： The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line or providing longitudinally spaced apart holes or vias to optimize the backflow potential capacity of the metal interconnection line. In addition, elongated slots are formed through the metal interconnection line so that the total width of metal across the interconnection line is selected for optimum electromigration lifetime in accordance with the Bamboo Effect for that metal.

摘要翻译： 金属互连线的电迁移寿命通过调整互连线的长度或提供纵向间隔开的孔或通孔来增加，以优化金属互连线的回流势能。 此外，通过金属互连线形成细长的槽，使得根据该金属的竹效应，选择跨越互连线的金属的总宽度以获得最佳的电迁移寿命。

公开(公告)号：US5136361A

公开(公告)日：1992-08-04

申请号：US338439

申请日：1989-04-13

申请人： Donald L. Wollesen ,  Craig S. Sander ,  Jacob D. Haskell

发明人： Donald L. Wollesen ,  Craig S. Sander ,  Jacob D. Haskell

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53223 ,  H01L21/76889 ,  H01L2924/0002

摘要： A low resistance interconnect structure for integrated circuits formed by a composite layer of aluminum below and an amorphous compound of refractory metal and silicon above. In the process of manufacturing the interconnect structure, care must be taken so that an aluminum oxide layer is not formed between the aluminum and compound layers.

摘要翻译： 由下面的铝复合层和难熔金属和硅的无定形化合物形成的用于集成电路的低电阻互连结构。 在制造互连结构的过程中，必须注意在铝和化合物层之间不形成氧化铝层。