公开(公告)号：US06596631B1

公开(公告)日：2003-07-22

申请号：US09626455

申请日：2000-07-26

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Lothar Mergili ,  Joerg Hohage ,  Lu You ,  Robert A. Huertas ,  Richard J. Huang

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Lothar Mergili ,  Joerg Hohage ,  Lu You ,  Robert A. Huertas ,  Richard J. Huang

IPC分类号： H01L244

CPC分类号： H01L21/76883 ,  H01L21/76834 ,  Y10S438/913

摘要： The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.

摘要翻译： 通过在处理暴露的平坦化表面之后延迟和/或缓慢地升高硅烷的引入以沉积氮化硅覆盖层来显着增强界面的完整性和阻挡层或覆盖层与Cu或Cu合金互连构件之间的粘合性 具有含氨等离子体的Cu或Cu合金。 其他实施方案包括在升高的温度下用氮气吹扫反应室以在引入用于等离子体处理的晶片之前去除残留气体。

公开(公告)号：US06368948B1

公开(公告)日：2002-04-09

申请号：US09626454

申请日：2000-07-26

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Joerg Hohage ,  Lothar Mergili

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Joerg Hohage ,  Lothar Mergili

IPC分类号： H01L2120

CPC分类号： H01L21/76838 ,  H01L21/76834

摘要： Reliably capped Cu interconnects are formed with a significant reduction in the amount and size of hillocks by reducing the time during which the Cu interconnect is exposed to elevated temperatures for plasma surface treatment and capping layer deposition. Embodiments of the present invention include maintaining a continuous plasma during surface treatment to remove copper oxide and capping layer deposition, and exposing the wafer to elevated temperatures to no greater than 60 seconds in the reaction chamber.

摘要翻译： 通过减少Cu互连暴露于升高的温度以进行等离子体表面处理和覆盖层沉积的时间，形成可靠的封盖的Cu互连，其显着减少了小丘的数量和尺寸。 本发明的实施例包括在表面处理期间保持连续等离子体以去除氧化铜和封盖层沉积，并将晶片暴露于升高的温度至不超过60秒的反应室中。

公开(公告)号：US06569768B2

公开(公告)日：2003-05-27

申请号：US09804657

申请日：2001-03-12

申请人： Hartmut Ruelke ,  Joerg Hohage ,  Minh Van Ngo

发明人： Hartmut Ruelke ,  Joerg Hohage ,  Minh Van Ngo

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/02074 ,  H01L21/3185 ,  H01L21/32136

摘要： A method for removing discoloration and corrosion of an exposed copper surface and for forming a nitride capping layer on top of the surface provides an in-situ process in which the reactive plasma ambient is constantly maintained during a transition from the surface treatment step to the deposition step for forming the nitride capping layer. Permanently maintained plasma avoids an renewed formation of discoloration on the cleaned copper surface during the transition to the deposition step and at the beginning of the deposition step when silane gas is introduced into the plasma ambient. Moreover, the overall process time is significantly reduced.

摘要翻译： 用于去除暴露的铜表面的变色和腐蚀并在表面顶部形成氮化物覆盖层的方法提供了一种原位工艺，其中反应性等离子体环境在从表面处理步骤转移到沉积期间始终保持 用于形成氮化物覆盖层的步骤。 永久维持的等离子体避免了在沉积步骤转变期间和沉积步骤开始时，在清洁的铜表面上，当将硅烷气体引入等离子体环境中时，会再次形成变色。 而且，总体处理时间显着减少。

公开(公告)号：US06221793B1

公开(公告)日：2001-04-24

申请号：US09517092

申请日：2000-03-01

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert A. Huertas

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612

摘要： A process for super low deposition rate plasma enhanced chemical vapor deposition (PECVD) of undoped oxide on a single station deposition is provided. A very thin PECVD oxide layer used, for instance, as an oxide liner between a polysilicon gate and a nitride spacer, may be produced in a PECVD chamber with a reduced flow rate of silane, nitrous oxide and molecular nitrogen. The deposition rate may be lowered to 20 angstroms/minute, for example, with this long deposition time providing a better process control. At the same time, the film is dense, silicon rich, highly compressive, provides excellent step coverage and acceptable thickness uniformity.

摘要翻译： 提供了一种用于单站沉积的超低沉积速率等离子体增强化学气相沉积（PECVD）未掺杂氧化物的方法。 例如，可以在具有降低的硅烷，一氧化二氮和分子氮的流速的PECVD室中产生非常薄的PECVD氧化物层，例如，作为多晶硅栅极和氮化物间隔物之间​​的氧化物衬垫。 沉积速率可以降低到20埃/分钟，例如，这种长的沉积时间提供更好的工艺控制。 同时，薄膜致密，富硅，高压缩，提供优异的台阶覆盖和可接受的厚度均匀性。

公开(公告)号：US06383925B1

公开(公告)日：2002-05-07

申请号：US09497850

申请日：2000-02-04

申请人： Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

发明人： Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

IPC分类号： H01L2144

CPC分类号： H01L21/76838 ,  H01L21/76834 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.

摘要翻译： 通过在具有氨和氮气的等离子体的反应室中处理Cu或Cu合金互连构件的CMP暴露表面之后，通过将Cu或Cu合金互连构件的阻挡层或覆盖层的粘合性显着提高， 一段时间以减少表面氧化物，然后将硅烷引入反应室，以在氮气存在下在高密度等离子体条件下沉积阻挡层，例如氮化硅。 在等离子体氧化物层还原和等离子体阻挡层沉积期间氮的存在显着提高了阻挡层对Cu或Cu合金表面的粘附性。

公开(公告)号：US06627973B1

公开(公告)日：2003-09-30

申请号：US10244129

申请日：2002-09-13

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

IPC分类号： H01L29167

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

公开(公告)号：US06489253B1

公开(公告)日：2002-12-03

申请号：US09788045

申请日：2001-02-16

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

IPC分类号： H01L21469

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

公开(公告)号：US06235654B1

公开(公告)日：2001-05-22

申请号：US09625511

申请日：2000-07-25

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert Huertas

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert Huertas

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  C23C16/345 ,  C23C16/402

摘要： A process for very low deposition rate plasma-enhanced chemical vapor deposition (PECVD) of nitride is provided. A nitride layer is used, for example, as a precursor for nitride spacers formed on the sidewalls of a polysilicon gate. The nitride layer may be produced in a PECVD chamber, using an increased flow rate of nitrogen applied to the chamber, an increased flow rate of molecular nitrogen, and a reduced flow rate of ammonia. The RF power is reduced, as well as the reactor pressure. This produces a nitride layer that exhibits improvements in density, refractive index, step coverage, and thickness non-unformity within a wafer and from wafer-to-wafer.

摘要翻译： 提供了氮化物的非常低的沉积速率等离子体增强化学气相沉积（PECVD）的方法。 氮化物层例如用作形成在多晶硅栅极的侧壁上的氮化物间隔物的前体。 氮化物层可以在PECVD室中使用增加的施加到室的氮的流速，分子氮的增加的流速和降低的氨的流速来生产。 RF功率降低，反应器压力降低。 这产生氮化物层，其在晶片和晶片到晶片内表现出密度，折射率，台阶覆盖率和厚度非不整度的改善。

公开(公告)号：US06599827B1

公开(公告)日：2003-07-29

申请号：US09846273

申请日：2001-05-02

申请人： Minh Van Ngo ,  Steven C. Avanzino ,  Amit P. Marathe ,  Hartmut Ruelke

发明人： Minh Van Ngo ,  Steven C. Avanzino ,  Amit P. Marathe ,  Hartmut Ruelke

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76883

摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by pumping out the deposition chamber after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma, introducing NH3 and N2 into the deposition chamber, and then ramping up the introduction of SiH4 prior to initiating deposition of a silicon nitride capping layer. Embodiments include ramping up the introduction of SiH4 in two stages prior to initiating plasma enhanced chemical vapor deposition of the silicon nitride capping layer.

摘要翻译： 通过在用含氨的等离子体处理暴露的Cu或Cu合金的平坦化表面之后，通过泵出沉积室来显着改善封盖的Cu或Cu合金互连的电迁移电阻，将NH 3和N 2引入沉积室，然后斜坡 在开始沉积氮化硅覆盖层之前引入SiH4。 实施例包括在引发氮化硅覆盖层的等离子体增强化学气相沉积之前分两阶段引入SiH4。

公开(公告)号：US07023046B2

公开(公告)日：2006-04-04

申请号：US10617450

申请日：2003-07-11

申请人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

发明人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625 ,  H01L27/115 ,  H01L29/511

摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

摘要翻译： 具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。 实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在 相同的沉积室。