公开(公告)号：US07023046B2

公开(公告)日：2006-04-04

申请号：US10617450

申请日：2003-07-11

申请人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

发明人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625 ,  H01L27/115 ,  H01L29/511

摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

摘要翻译： 具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。 实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在 相同的沉积室。

公开(公告)号：US06774432B1

公开(公告)日：2004-08-10

申请号：US10358589

申请日：2003-02-05

申请人： Minh V. Ngo ,  Tazrien Kamal ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Jaeyong Park ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Jeffrey A. Shields ,  Angela T. Hui ,  Robert A. Huertas ,  Tyagamohan Gottipati

发明人： Minh V. Ngo ,  Tazrien Kamal ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Jaeyong Park ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Jeffrey A. Shields ,  Angela T. Hui ,  Robert A. Huertas ,  Tyagamohan Gottipati

IPC分类号： H01L29792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L23/552 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  Y10S438/954 ,  H01L2924/00

摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.

摘要翻译： 一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。 SONOS闪存设备，包括SONOS闪存单元; 以及至少一个UV保护层，其中UV保护层包括基本上不透紫外线的材料。 在一个实施例中，该装置包括基本上不透紫外线的接触盖层。

公开(公告)号：US07018896B2

公开(公告)日：2006-03-28

申请号：US10818112

申请日：2004-04-05

申请人： Minh V. Ngo ,  Tazrien Kamal ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Jaeyong Park ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Jeffrey A. Shields ,  Angela T. Hui ,  Robert A. Huertas ,  Tyagamohan Gottipati

发明人： Minh V. Ngo ,  Tazrien Kamal ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Jaeyong Park ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Jeffrey A. Shields ,  Angela T. Hui ,  Robert A. Huertas ,  Tyagamohan Gottipati

IPC分类号： H01L21/00

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L23/552 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  Y10S438/954 ,  H01L2924/00

摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.

摘要翻译： 一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。 在一个实施例中，该装置包括接触帽层或基本上不透紫外线的接触覆盖层的基本不透紫外不透明的子层。

公开(公告)号：US07300886B1

公开(公告)日：2007-11-27

申请号：US11147208

申请日：2005-06-08

申请人： Minh Van Ngo ,  Ning Cheng ,  Wenmei Li ,  Angela T. Hui ,  Pei-Yuan Gao ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Ning Cheng ,  Wenmei Li ,  Angela T. Hui ,  Pei-Yuan Gao ,  Robert A. Huertas

IPC分类号： H01L21/31

CPC分类号： H01L21/31625 ,  H01L21/02129 ,  H01L21/02271 ,  H01L27/115 ,  H01L27/11568

摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.

摘要翻译： 一种制造存储器件的方法包括在衬底上形成第一介电层，并在第一介电层上形成电荷存储元件。 该方法还包括在电荷存储元件上形成第二电介质层，并在第二电介质层上形成控制栅极。 该方法还包括在高温下在控制栅极上沉积层间电介质。

公开(公告)号：US06627973B1

公开(公告)日：2003-09-30

申请号：US10244129

申请日：2002-09-13

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

IPC分类号： H01L29167

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

公开(公告)号：US06489253B1

公开(公告)日：2002-12-03

申请号：US09788045

申请日：2001-02-16

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

IPC分类号： H01L21469

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

公开(公告)号：US06596631B1

公开(公告)日：2003-07-22

申请号：US09626455

申请日：2000-07-26

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Lothar Mergili ,  Joerg Hohage ,  Lu You ,  Robert A. Huertas ,  Richard J. Huang

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Lothar Mergili ,  Joerg Hohage ,  Lu You ,  Robert A. Huertas ,  Richard J. Huang

IPC分类号： H01L244

CPC分类号： H01L21/76883 ,  H01L21/76834 ,  Y10S438/913

摘要： The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.

摘要翻译： 通过在处理暴露的平坦化表面之后延迟和/或缓慢地升高硅烷的引入以沉积氮化硅覆盖层来显着增强界面的完整性和阻挡层或覆盖层与Cu或Cu合金互连构件之间的粘合性 具有含氨等离子体的Cu或Cu合金。 其他实施方案包括在升高的温度下用氮气吹扫反应室以在引入用于等离子体处理的晶片之前去除残留气体。

公开(公告)号：US06388330B1

公开(公告)日：2002-05-14

申请号：US09776012

申请日：2001-02-01

申请人： Minh Van Ngo ,  Dawn M. Hopper ,  Robert A. Huertas ,  Terri J. Kitson

发明人： Minh Van Ngo ,  Dawn M. Hopper ,  Robert A. Huertas ,  Terri J. Kitson

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L21/76801 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.

摘要翻译： 因此，提供了具有半导体衬底和半导体器件的集成电路和制造方法，所述半导体衬底具有半导体衬底上的介电层。 导体芯填充电介质层中的开口。 在第一介电层和导体芯上形成介电常数低于5.5的蚀刻停止层。 蚀刻停止层上的第二电介质层具有提供给导体芯的开口。 第二导体芯填充第二开口并连接到第一导体芯。

公开(公告)号：US06383880B1

公开(公告)日：2002-05-07

申请号：US09679374

申请日：2000-10-05

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Robert A. Huertas

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/3105

摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用包含氨和氮的等离子体处理氮化硅侧壁间隔物的暴露表面以产生具有增加的氮的清洁表面区域来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氨和氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06809043B1

公开(公告)日：2004-10-26

申请号：US10173611

申请日：2002-06-19

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Hieu Pham

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Hieu Pham

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28247 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612

摘要： A silicon oxide layer is deposited at a thickness of about 50 Å or less by a multi-stage method comprising depositing a sub-layer of silicon oxide in each stage by PECVD at a low deposition rate. Embodiments include depositing a silicon dioxide liner over a gate electrode in at least four stages, each stage comprising depositing a sub-layer at a thickness of 10 Å or less.

摘要翻译： 氧化硅层通过多级方法沉积在大约等于或小于50埃的厚度，包括通过PECVD以低沉积速率在每个阶段沉积氧化硅的子层。 实施例包括在至少四个阶段中在栅电极上沉积二氧化硅衬垫，每个阶段包括沉积厚度为或更小的子层。