公开(公告)号：US06235654B1

公开(公告)日：2001-05-22

申请号：US09625511

申请日：2000-07-25

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert Huertas

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert Huertas

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  C23C16/345 ,  C23C16/402

摘要： A process for very low deposition rate plasma-enhanced chemical vapor deposition (PECVD) of nitride is provided. A nitride layer is used, for example, as a precursor for nitride spacers formed on the sidewalls of a polysilicon gate. The nitride layer may be produced in a PECVD chamber, using an increased flow rate of nitrogen applied to the chamber, an increased flow rate of molecular nitrogen, and a reduced flow rate of ammonia. The RF power is reduced, as well as the reactor pressure. This produces a nitride layer that exhibits improvements in density, refractive index, step coverage, and thickness non-unformity within a wafer and from wafer-to-wafer.

摘要翻译： 提供了氮化物的非常低的沉积速率等离子体增强化学气相沉积（PECVD）的方法。 氮化物层例如用作形成在多晶硅栅极的侧壁上的氮化物间隔物的前体。 氮化物层可以在PECVD室中使用增加的施加到室的氮的流速，分子氮的增加的流速和降低的氨的流速来生产。 RF功率降低，反应器压力降低。 这产生氮化物层，其在晶片和晶片到晶片内表现出密度，折射率，台阶覆盖率和厚度非不整度的改善。

公开(公告)号：US06569768B2

公开(公告)日：2003-05-27

申请号：US09804657

申请日：2001-03-12

申请人： Hartmut Ruelke ,  Joerg Hohage ,  Minh Van Ngo

发明人： Hartmut Ruelke ,  Joerg Hohage ,  Minh Van Ngo

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/02074 ,  H01L21/3185 ,  H01L21/32136

摘要： A method for removing discoloration and corrosion of an exposed copper surface and for forming a nitride capping layer on top of the surface provides an in-situ process in which the reactive plasma ambient is constantly maintained during a transition from the surface treatment step to the deposition step for forming the nitride capping layer. Permanently maintained plasma avoids an renewed formation of discoloration on the cleaned copper surface during the transition to the deposition step and at the beginning of the deposition step when silane gas is introduced into the plasma ambient. Moreover, the overall process time is significantly reduced.

摘要翻译： 用于去除暴露的铜表面的变色和腐蚀并在表面顶部形成氮化物覆盖层的方法提供了一种原位工艺，其中反应性等离子体环境在从表面处理步骤转移到沉积期间始终保持 用于形成氮化物覆盖层的步骤。 永久维持的等离子体避免了在沉积步骤转变期间和沉积步骤开始时，在清洁的铜表面上，当将硅烷气体引入等离子体环境中时，会再次形成变色。 而且，总体处理时间显着减少。

公开(公告)号：US06221793B1

公开(公告)日：2001-04-24

申请号：US09517092

申请日：2000-03-01

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert A. Huertas

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612

摘要： A process for super low deposition rate plasma enhanced chemical vapor deposition (PECVD) of undoped oxide on a single station deposition is provided. A very thin PECVD oxide layer used, for instance, as an oxide liner between a polysilicon gate and a nitride spacer, may be produced in a PECVD chamber with a reduced flow rate of silane, nitrous oxide and molecular nitrogen. The deposition rate may be lowered to 20 angstroms/minute, for example, with this long deposition time providing a better process control. At the same time, the film is dense, silicon rich, highly compressive, provides excellent step coverage and acceptable thickness uniformity.

摘要翻译： 提供了一种用于单站沉积的超低沉积速率等离子体增强化学气相沉积（PECVD）未掺杂氧化物的方法。 例如，可以在具有降低的硅烷，一氧化二氮和分子氮的流速的PECVD室中产生非常薄的PECVD氧化物层，例如，作为多晶硅栅极和氮化物间隔物之间​​的氧化物衬垫。 沉积速率可以降低到20埃/分钟，例如，这种长的沉积时间提供更好的工艺控制。 同时，薄膜致密，富硅，高压缩，提供优异的台阶覆盖和可接受的厚度均匀性。

公开(公告)号：US06596631B1

公开(公告)日：2003-07-22

申请号：US09626455

申请日：2000-07-26

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Lothar Mergili ,  Joerg Hohage ,  Lu You ,  Robert A. Huertas ,  Richard J. Huang

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Lothar Mergili ,  Joerg Hohage ,  Lu You ,  Robert A. Huertas ,  Richard J. Huang

IPC分类号： H01L244

CPC分类号： H01L21/76883 ,  H01L21/76834 ,  Y10S438/913

摘要： The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.

摘要翻译： 通过在处理暴露的平坦化表面之后延迟和/或缓慢地升高硅烷的引入以沉积氮化硅覆盖层来显着增强界面的完整性和阻挡层或覆盖层与Cu或Cu合金互连构件之间的粘合性 具有含氨等离子体的Cu或Cu合金。 其他实施方案包括在升高的温度下用氮气吹扫反应室以在引入用于等离子体处理的晶片之前去除残留气体。

公开(公告)号：US06368948B1

公开(公告)日：2002-04-09

申请号：US09626454

申请日：2000-07-26

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Joerg Hohage ,  Lothar Mergili

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Joerg Hohage ,  Lothar Mergili

IPC分类号： H01L2120

CPC分类号： H01L21/76838 ,  H01L21/76834

摘要： Reliably capped Cu interconnects are formed with a significant reduction in the amount and size of hillocks by reducing the time during which the Cu interconnect is exposed to elevated temperatures for plasma surface treatment and capping layer deposition. Embodiments of the present invention include maintaining a continuous plasma during surface treatment to remove copper oxide and capping layer deposition, and exposing the wafer to elevated temperatures to no greater than 60 seconds in the reaction chamber.

摘要翻译： 通过减少Cu互连暴露于升高的温度以进行等离子体表面处理和覆盖层沉积的时间，形成可靠的封盖的Cu互连，其显着减少了小丘的数量和尺寸。 本发明的实施例包括在表面处理期间保持连续等离子体以去除氧化铜和封盖层沉积，并将晶片暴露于升高的温度至不超过60秒的反应室中。

公开(公告)号：US06599827B1

公开(公告)日：2003-07-29

申请号：US09846273

申请日：2001-05-02

申请人： Minh Van Ngo ,  Steven C. Avanzino ,  Amit P. Marathe ,  Hartmut Ruelke

发明人： Minh Van Ngo ,  Steven C. Avanzino ,  Amit P. Marathe ,  Hartmut Ruelke

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76883

摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by pumping out the deposition chamber after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma, introducing NH3 and N2 into the deposition chamber, and then ramping up the introduction of SiH4 prior to initiating deposition of a silicon nitride capping layer. Embodiments include ramping up the introduction of SiH4 in two stages prior to initiating plasma enhanced chemical vapor deposition of the silicon nitride capping layer.

摘要翻译： 通过在用含氨的等离子体处理暴露的Cu或Cu合金的平坦化表面之后，通过泵出沉积室来显着改善封盖的Cu或Cu合金互连的电迁移电阻，将NH 3和N 2引入沉积室，然后斜坡 在开始沉积氮化硅覆盖层之前引入SiH4。 实施例包括在引发氮化硅覆盖层的等离子体增强化学气相沉积之前分两阶段引入SiH4。

公开(公告)号：US06506677B1

公开(公告)日：2003-01-14

申请号：US09846186

申请日：2001-05-02

申请人： Steven C. Avanzino ,  Minh Van Ngo ,  Amit P. Marathe ,  Hartmut Ruelke

发明人： Steven C. Avanzino ,  Minh Van Ngo ,  Amit P. Marathe ,  Hartmut Ruelke

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76883

摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of SiH4 and then initiating deposition of a silicon nitride capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, ramping up the introduction of SiH4 in two stages, and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure, N2 flow rate and NH3 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

摘要翻译： 通过用含有NH 3和N 2的等离子体依次和连续地处理埋入Cu的暴露的平坦化表面，显着改善了封盖的Cu或Cu合金互连的电迁移阻力，增加引入SiH 4，然后开始沉积氮化硅封盖 层。 实施方案包括用用N 2稀释的软NH 3等离子体处理嵌入的Cu的暴露表面，分两步引入SiH4，然后启动氮化硅覆盖层的等离子体增强化学气相沉积，同时保持基本相同 压力，N2流量和等离子体处理期间的NH3流量，SiH4斜坡上升和氮化硅沉积。 实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

公开(公告)号：US07534732B1

公开(公告)日：2009-05-19

申请号：US11356311

申请日：2006-02-17

申请人： Minh Van Ngo ,  Erik Wilson ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

发明人： Minh Van Ngo ,  Erik Wilson ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L21/0217 ,  C23C16/345 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11568

摘要： Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.

摘要翻译： Cu互连形成有用于减少电迁移的复合覆盖层，Cu和覆盖层之间改善的粘附性，以及相关联的非易失性晶体管中的减少的电荷损失。 实施例包括在Cu层的上表面上沉积具有较高浓度的Si-H键的第一相对较薄的氮化硅层，以改善粘附性和减少电迁移，以及沉积具有较低浓度的第二较厚的氮化硅层 的Si-H键在第一氮化硅层上以减少电荷损失。

公开(公告)号：US08415256B1

公开(公告)日：2013-04-09

申请号：US12982364

申请日：2010-12-30

申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。

公开(公告)号：US07884030B1

公开(公告)日：2011-02-08

申请号：US11408086

申请日：2006-04-21

申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L23/58

CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。