公开(公告)号：US06957378B2

公开(公告)日：2005-10-18

申请号：US10162414

申请日：2002-06-03

申请人： Mitsuhiro Koga ,  Munehiro Yoshida ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Munehiro Yoshida ,  Hiroshi Shinya

IPC分类号： G06F11/10 ,  G11C7/24 ,  G11C11/4078 ,  G11C29/00

CPC分类号： G06F11/1032 ,  G11C7/24 ,  G11C11/4078

摘要： A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m

摘要翻译： 公开了一种半导体存储器件，其包括一个单元阵列，该单元阵列包括用于正常数据写入和读取的正常数据段和用于校验数据写入和读取的奇偶校验数据段，该校验数据用于执行读出数据的错误校验 正常数据部分的数据缓冲器，用于从单元阵列读取数据的时间阶段的数据缓冲器，并将数据写入单元阵列;以及ECC电路，用于从作为输入的写数据产生要存储在奇偶校验数据部分中的校验数据 数据写入，并且用于在数据读取期间，基于从正常数据部分读出的数据和从所述奇偶校验数据部分读出的检查数据，对从普通部分读出的数据执行错误检查和校正。 在数据缓冲器和正常数据部分之间执行N位并行数据传输，而在数据缓冲器和外部输入/输出端子之间进行m位并行数据传输（其中m和n是满足m

公开(公告)号：US06570801B2

公开(公告)日：2003-05-27

申请号：US09981517

申请日：2001-10-16

申请人： Munehiro Yoshida ,  Hiroshi Shinya

发明人： Munehiro Yoshida ,  Hiroshi Shinya

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： An internal row address signal is generated by a refresh address counter and supplied to a row decoder. In a normal refresh operation, the refresh address counter sequentially increments the internal row address signal on the basis of a trigger signal. As a result, the data in all memory cells is refreshed. In a low-consumption-current refresh operation, at least one of the bits of the internal row address signal is fixed. Hence, the refresh operation is executed only for the memory cells of a predetermined refresh area.

公开(公告)号：US06876588B2

公开(公告)日：2005-04-05

申请号：US10664464

申请日：2003-09-17

申请人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

发明人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

IPC分类号： G11C8/02 ,  G11C29/00 ,  G11C29/26 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/26 ,  G11C29/787 ,  G11C2029/2602

摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

公开(公告)号：US06646932B2

公开(公告)日：2003-11-11

申请号：US10162433

申请日：2002-06-03

申请人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

发明人： Daisuke Kato ,  Munehiro Yoshida ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/785

摘要： A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair region as group of first/second normal elements with permission of replacement by each first/second redundant element.

摘要翻译： 半导体存储器件具有单元阵列，每个在单元阵列内定义的第一法向元件作为沿单元阵列的第一方向布置的一组存储单元，每个在单元阵列内被定义为一组存储单元，每个存储单元被布置 在所述单元阵列的第二方向上，每个所述第二普通元件选择与所述第一正常元件中的对应的一个操作关联的存储器单元，用于替换所述单元阵列内的有缺陷的第一正常元件的第一冗余元件和所述第二冗余元件 用于替换电池阵列内的有缺陷的第二正常元件的元件。 在单元阵列第一/第二修复区域内被定义为具有第一/第二正常元素的组，并且允许由每个第一/第二冗余元素替换。

公开(公告)号：US07102417B2

公开(公告)日：2006-09-05

申请号：US10982019

申请日：2004-11-05

申请人： Melia F. Gordon ,  Charles Ray Johns ,  Hiroki Kihara ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Michael Fan Wang ,  Kazuaki Yazawa ,  Munehiro Yoshida

发明人： Melia F. Gordon ,  Charles Ray Johns ,  Hiroki Kihara ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Michael Fan Wang ,  Kazuaki Yazawa ,  Munehiro Yoshida

IPC分类号： H03K17/78

CPC分类号： G01K15/00 ,  G01R31/2856 ,  G01R31/2874 ,  G01R31/31704 ,  G01R31/319 ,  G01R31/31908

摘要： An integrated circuit die is disclosed including a temperature detection circuit and a memory configured to store calibration data. The temperature detection circuit is operatively coupled to the memory, and receives an input signal. The temperature detection circuit is configured to produce an output signal dependent upon the input signal and indicative of whether a temperature of the integrated circuit die is greater than a selected temperature. During a normal operating mode of the integrated circuit die the input signal comprises the calibration data. A system and methods for calibrating the temperature detection circuit are also described.

摘要翻译： 公开了一种集成电路管芯，其包括温度检测电路和配置为存储校准数据的存储器。 温度检测电路可操作地耦合到存储器，并且接收输入信号。 温度检测电路被配置为根据输入信号产生输出信号，并且指示集成电路管芯的温度是否大于所选择的温度。 在集成电路管芯的正常操作模式期间，输入信号包括校准数据。 还描述了用于校准温度检测电路的系统和方法。

公开(公告)号：US20060153277A1

公开(公告)日：2006-07-13

申请号：US11034644

申请日：2005-01-13

申请人： Munehiro Yoshida

发明人： Munehiro Yoshida

IPC分类号： G01K7/00

CPC分类号： G01K3/005 ,  G01K7/01

摘要： Systems and methods for reducing the complexity and size of thermal sensors, where the voltage of a thermally sensitive device is compared to a reference voltage that varies as a function of temperature, rather than being constant. One embodiment comprises a thermal sensing system including a reference voltage generator, a thermal sensor and a comparator. The reference voltage generator is configured to generate a non-constant reference voltage that varies as a known function of temperature. The thermal sensor is configured to generate a sensor voltage that also varies as a known function of temperature. The functions of the reference and sensor voltages cross at a known temperature/voltage. The comparator is configured to compare the sensor voltage and the reference voltage and to generate a comparison output signal based on the comparison of the sensor voltage and the first reference voltage. A transition in this signal indicates the reference temperature.

摘要翻译： 用于降低热传感器的复杂性和尺寸的系统和方法，其中将热敏元件的电压与作为温度的函数变化的参考电压进行比较，而不是恒定。 一个实施例包括包括参考电压发生器，热传感器和比较器的热感测系统。 参考电压发生器被配置为产生作为已知温度函数而变化的非恒定参考电压。 热传感器被配置为产生也随温度已知功能而变化的传感器电压。 参考电压和传感器电压的功能在已知的温度/电压下交叉。 比较器被配置为比较传感器电压和参考电压，并且基于传感器电压和第一参考电压的比较来产生比较输出信号。 此信号中的转换表示参考温度。

公开(公告)号：US6063131A

公开(公告)日：2000-05-16

申请号：US948520

申请日：1997-10-10

申请人： Munehiro Yoshida

发明人： Munehiro Yoshida

IPC分类号： G06F11/34 ,  G06F11/22 ,  G06F11/26 ,  G06F11/36 ,  G06F9/455

CPC分类号： G06F11/3636 ,  G06F11/261 ,  G06F11/3656

摘要： An emulator system solving a problem of conventional emulator systems by recognizing a task execution history. In conventional systems, it was necessary for a microcomputer to incorporate a specific task for storing in a memory an identification number and switching time of a task to be executed next in a program to be debugged. The novel emulator system includes a first detector for detecting a write cycle of a microcomputer in which the identification number of a task to be executed next is recorded. A second detector detects the start cycle and end cycle of an interrupt. A measurement memory stores the timing of the write cycle and the timing of the start cycle and end cycle of the interrupt.

摘要翻译： 通过识别任务执行历史来解决常规仿真器系统的问题的仿真器系统。 在常规系统中，微型计算机需要将待调试的程序中的下一个要执行的任务的识别号码和切换时间存入存储器的特定任务。 该新颖的仿真器系统包括：第一检测器，用于检测其中记录下一个要执行的任务的识别号码的微型计算机的写入周期。 第二个检测器检测中断的起始周期和结束周期。 测量存储器存储写周期的定时和中断的起始周期和结束周期的定时。

公开(公告)号：US5110750A

公开(公告)日：1992-05-05

申请号：US561608

申请日：1990-08-02

申请人： Munehiro Yoshida

发明人： Munehiro Yoshida

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L27/092 ,  H01L29/10

CPC分类号： H01L29/107

摘要： For compensating a decreased impurity concentration at a peripheral portion of a well region provided in a semiconductor substrate, an impurity whose conductivity type is same as that of the well region is diffused into the peripheral portion thereof to form a diffused region thereon. Therefore, the well region having the approximately uniform surface impurity concentration is provided.

公开(公告)号：US20070150225A1

公开(公告)日：2007-06-28

申请号：US11682145

申请日：2007-03-05

申请人： David Boerstler ,  Munehiro Yoshida

发明人： David Boerstler ,  Munehiro Yoshida

IPC分类号： G01K1/08

CPC分类号： H01L27/0248 ,  G01K1/026 ,  G01K3/14 ,  G01K7/01

摘要： The present invention provides a method for determining a hot area of an integrated circuit. A first temperature sensor in a first area of a chip is read, the chip comprising a plurality of chip areas, wherein the first area is a comparison area. The comparison area comprises at least one I/O device that is controlled to simulate other functional I/O devices on the chip. A second temperature sensor in a second area of a chip is read. The readings of the first temperature sensor and the second temperature sensor are compared. If the difference between the first temperature reading and the second temperature reading exceeds a threshold, a first error condition is indicated.

摘要翻译： 本发明提供了一种用于确定集成电路的热区的方法。 读取芯片的第一区域中的第一温度传感器，该芯片包括多个芯片区域，其中第一区域是比较区域。 比较区域包括至少一个被控制以模拟芯片上的其他功能I / O设备的I / O设备。 读取芯片的第二区域中的第二温度传感器。 比较第一温度传感器和第二温度传感器的读数。 如果第一温度读数和第二温度读数之间的差超过阈值，则指示第一错误状态。

公开(公告)号：US20060192597A1

公开(公告)日：2006-08-31

申请号：US11052495

申请日：2005-02-04

申请人： Charles Johns ,  Michael Wang ,  Munehiro Yoshida

发明人： Charles Johns ,  Michael Wang ,  Munehiro Yoshida

IPC分类号： H03K5/22 ,  H03K5/153

CPC分类号： G01K7/425 ,  G01K1/026 ,  G01K7/01

摘要： Temperature sensing circuits are disclosed. One embodiment of a temperature sensing circuit includes a voltage divider and an analog multiplexer. The voltage divider network divides an analog voltage into multiple derived analog voltages. The analog multiplexer receives at least two of the derived analog voltages and a control signal, and is configured to produce one of the received derived analog voltages dependent upon the control signal. Temperature detection circuits including the temperature sensing circuits are also disclosed.

摘要翻译： 公开了温度感测电路。 温度感测电路的一个实施例包括分压器和模拟多路复用器。 分压网络将模拟电压分为多个衍生的模拟电压。 模拟多路复用器接收导出的模拟电压和控制信号中的至少两个，并且被配置为根据控制信号产生接收的导出的模拟电压之一。 还公开了包括温度检测电路的温度检测电路。