公开(公告)号：US06957378B2

公开(公告)日：2005-10-18

申请号：US10162414

申请日：2002-06-03

申请人： Mitsuhiro Koga ,  Munehiro Yoshida ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Munehiro Yoshida ,  Hiroshi Shinya

IPC分类号： G06F11/10 ,  G11C7/24 ,  G11C11/4078 ,  G11C29/00

CPC分类号： G06F11/1032 ,  G11C7/24 ,  G11C11/4078

摘要： A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m

摘要翻译： 公开了一种半导体存储器件，其包括一个单元阵列，该单元阵列包括用于正常数据写入和读取的正常数据段和用于校验数据写入和读取的奇偶校验数据段，该校验数据用于执行读出数据的错误校验 正常数据部分的数据缓冲器，用于从单元阵列读取数据的时间阶段的数据缓冲器，并将数据写入单元阵列;以及ECC电路，用于从作为输入的写数据产生要存储在奇偶校验数据部分中的校验数据 数据写入，并且用于在数据读取期间，基于从正常数据部分读出的数据和从所述奇偶校验数据部分读出的检查数据，对从普通部分读出的数据执行错误检查和校正。 在数据缓冲器和正常数据部分之间执行N位并行数据传输，而在数据缓冲器和外部输入/输出端子之间进行m位并行数据传输（其中m和n是满足m

公开(公告)号：US20070067699A1

公开(公告)日：2007-03-22

申请号：US11512145

申请日：2006-08-30

申请人： Mitsuhiro Koga ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Hiroshi Shinya

IPC分类号： G11C29/00

CPC分类号： G11C29/20 ,  G06F11/1048 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C29/1201 ,  G11C29/36 ,  G11C29/42 ,  G11C2029/0407 ,  G11C2029/0411 ,  G11C2029/3602 ,  G11C2211/4062

摘要： A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O buffer outputs N-bit data. The I/O buffer inputs N-bit data to the read/write buffer, and the read/write buffer outputs N-bit data to the I/O buffer. The memory cell array inputs up to M×N-bit data to the read/write buffer, and the read/write buffer outputs up to M×N-bit data to the memory cell array. The read/write buffer writes a variable number of bits to the memory cell array (N is a natural number equal to or larger than 1, and M is a natural number equal to or larger than 2).

摘要翻译： 公开了一种半导体集成电路器件。 该装置包括存储单元阵列，I / O缓冲器，读/写缓冲器，错误检查和校正电路以及初始化检查电路。 N位数据输入到I / O缓冲器，I / O缓冲器输出N位数据。 I / O缓冲器将N位数据输入到读/写缓冲器，读/写缓冲器将N位数据输出到I / O缓冲器。 存储单元阵列将高达MxN位数据输入到读/写缓冲器，读/写缓冲器向存储单元阵列输出高达MxN位的数据。 读/写缓冲器将可变数目的位写入存储单元阵列（N是等于或大于1的自然数，M是等于或大于2的自然数）。

公开(公告)号：US07266759B2

公开(公告)日：2007-09-04

申请号：US10878229

申请日：2004-06-29

申请人： Mitsuhiro Koga ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Hiroshi Shinya

IPC分类号： G11C29/00

CPC分类号： G06F11/1008 ,  G06F2211/109 ,  G11C7/1006 ,  G11C7/1027 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4096 ,  G11C2211/4062 ,  H03M13/09

摘要： A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

摘要翻译： 一种半导体集成电路装置，包括：存储单元阵列，错误检查和校正（ECC）电路，其在读取等待时间期间的数据读出时间执行从正常数据存储部分读出的读出数据的错误检查和校正操作，以及I / O缓冲区。 存储单元阵列包括正常数据存储部分和奇偶校验数据存储部分。 正常数据存储部分存储用于正常数据写入和正常数据读取的数据。 奇偶校验数据存储部存储用于错误检查和校正的奇偶校验数据。 在数据读取操作的读取延迟周期期间，EEC电路执行错误检查和校正从正常数据存储部分读出的读取数据。 在读取延迟周期过后，I / O缓冲器输出由ECC电路检查并校正的读取数据错误。

公开(公告)号：US07385849B2

公开(公告)日：2008-06-10

申请号：US11512145

申请日：2006-08-30

申请人： Mitsuhiro Koga ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Hiroshi Shinya

IPC分类号： G11C11/34

CPC分类号： G11C29/20 ,  G06F11/1048 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C29/1201 ,  G11C29/36 ,  G11C29/42 ,  G11C2029/0407 ,  G11C2029/0411 ,  G11C2029/3602 ,  G11C2211/4062

摘要： A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O buffer outputs N-bit data. The I/O buffer inputs N-bit data to the read/write buffer, and the read/write buffer outputs N-bit data to the I/O buffer. The memory cell array inputs up to M×N-bit data to the read/write buffer, and the read/write buffer outputs up to M×N-bit data to the memory cell array. The read/write buffer writes a variable number of bits to the memory cell array (N is a natural number equal to or larger than 1, and M is a natural number equal to or larger than 2).

摘要翻译： 公开了一种半导体集成电路器件。 该装置包括存储单元阵列，I / O缓冲器，读/写缓冲器，错误检查和校正电路以及初始化检查电路。 N位数据输入到I / O缓冲器，I / O缓冲器输出N位数据。 I / O缓冲器将N位数据输入到读/写缓冲器，读/写缓冲器将N位数据输出到I / O缓冲器。 存储单元阵列将高达MxN位数据输入到读/写缓冲器，读/写缓冲器向存储单元阵列输出高达MxN位的数据。 读/写缓冲器将可变数目的位写入存储单元阵列（N是等于或大于1的自然数，M是等于或大于2的自然数）。

公开(公告)号：US20050005230A1

公开(公告)日：2005-01-06

申请号：US10878229

申请日：2004-06-29

申请人： Mitsuhiro Koga ,  Hiroshi Shinya

发明人： Mitsuhiro Koga ,  Hiroshi Shinya

IPC分类号： G06F11/10 ,  G06F7/02 ,  G06F11/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/42 ,  H03M13/00 ,  H03M13/09

CPC分类号： G06F11/1008 ,  G06F2211/109 ,  G11C7/1006 ,  G11C7/1027 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4096 ,  G11C2211/4062 ,  H03M13/09

摘要： A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

摘要翻译： 一种半导体集成电路装置，包括：存储单元阵列，错误检查和校正（ECC）电路，其在读取等待时间期间的数据读出时间执行从正常数据存储部分读出的读出数据的错误检查和校正操作，以及I / O缓冲区。 存储单元阵列包括正常数据存储部分和奇偶校验数据存储部分。 正常数据存储部分存储用于正常数据写入和正常数据读取的数据。 奇偶校验数据存储部存储用于错误检查和校正的奇偶校验数据。 在数据读取操作的读取延迟周期期间，EEC电路执行错误检查和校正从正常数据存储部分读出的读取数据。 在读取延迟周期过后，I / O缓冲器输出由ECC电路检查并校正的读取数据错误。

公开(公告)号：US08102092B2

公开(公告)日：2012-01-24

申请号：US12161931

申请日：2007-01-19

申请人： Kenji Tomohara ,  Seiji Miyazaki ,  Mitsuhiro Koga ,  Makoto Matsumoto ,  Hiroshi Koga ,  Shinichi Sakamoto

发明人： Kenji Tomohara ,  Seiji Miyazaki ,  Mitsuhiro Koga ,  Makoto Matsumoto ,  Hiroshi Koga ,  Shinichi Sakamoto

IPC分类号： H02K1/06

CPC分类号： H02K1/148 ,  H02K15/022 ,  H02K2201/06 ,  Y10T29/49009

摘要： Split cores comprising laminated iron cores each having formed thereon a tooth, and a yoke and a pole piece which are connected to the tooth at both ends thereof, and arranged and connected together into an annular shape to make a stator. Both ends of the yokes and both ends of the pole pieces are displaced in one circumferential direction by laminated iron core from a top laminated layer of the iron cores of the split cores to a bottom laminated layer of the iron cores or split cores.

摘要翻译： 分离芯包括各自形成有齿的层叠铁芯，以及轭和极片，其两端连接到齿，并且被布置并连接在一起成环形以形成定子。 磁轭的两端和磁极片的两端在一个圆周方向上通过层叠的铁芯从分裂芯的铁芯的顶层叠层向铁芯或分裂芯的底层叠层移位。

公开(公告)号：US20090026872A1

公开(公告)日：2009-01-29

申请号：US12161931

申请日：2007-01-19

申请人： Kenji Tomohara ,  Seiji Miyazaki ,  Mitsuhiro Koga ,  Makoto Matsumoto ,  Hiroshi Koga ,  Shinichi Sakamoto

发明人： Kenji Tomohara ,  Seiji Miyazaki ,  Mitsuhiro Koga ,  Makoto Matsumoto ,  Hiroshi Koga ,  Shinichi Sakamoto

IPC分类号： H02K1/12 ,  H02K15/02

CPC分类号： H02K1/148 ,  H02K15/022 ,  H02K2201/06 ,  Y10T29/49009

摘要： Although in a conventional permanent magnet type synchronous motor, cogging torque is reduced by displacing permanent magnets of a rotor in a circumferential direction or displacing a stator core in a circumferential direction, since the skew so produced reduces the output of the motor and moreover the winding work of windings cannot be automated to make the resulting motor highly expensive, split cores are provided which solves those problems and enables the winding work of windings to be automated so as to obtain an inexpensive and high-output motor.There are provided a plurality of split cores (100) made up of laminated iron cores each having formed thereon a tooth (6), and a yoke (5) and a pole piece (9) which are made to connect to the tooth (6) at both ends thereof, and arranged and connected together into an annular shape to make up a stator, characterized in that both ends of the yokes (5) and both ends of the pole pieces (9) are displaced in one circumferential direction by laminated iron core from a top laminated layer to a bottom laminated layer of the iron cores of the split cores.

摘要翻译： 虽然在传统的永久磁铁式同步电动机中，通过沿圆周方向移动转子的永磁体或使定子铁芯在圆周方向上移位来减小齿槽转矩，但由于产生的倾斜减小了电动机的输出，而且绕组 绕组的工作不能自动化，使得所得到的电动机非常昂贵，提供了解决这些问题的分裂芯，并且使绕组的绕组工作能够自动化，从而获得廉价且高输出的电动机。 设置有多个由分别形成有齿（6）的层叠铁芯构成的分割芯（100）和与齿（6）连接的轭（5）和极片（9） ），并且布置并连接在一起形成环形以构成定子，其特征在于，磁轭（5）的两端和磁极片（9）的两端通过层叠在一个圆周方向上位移 铁芯从顶层叠层到分裂芯的铁芯的底层叠层。

公开(公告)号：US07329971B2

公开(公告)日：2008-02-12

申请号：US10516689

申请日：2003-06-05

申请人： Haruki Yahara ,  Makoto Matsumoto ,  Mitsuhiro Koga ,  Mitsuhiro Matsuzaki

发明人： Haruki Yahara ,  Makoto Matsumoto ,  Mitsuhiro Koga ,  Mitsuhiro Matsuzaki

IPC分类号： H02K41/00

CPC分类号： H02K41/0356

摘要： A voice coil type linear motor with a cooling function. A closed magnetic circuit formed into the θ-shape, by an inner yoke provided between a pair of outer yokes made up of magnetic materials arranged in parallel with a longitudinal center axis in such a manner as to be in parallel with the pair of outer yokes. The outer yokes and side yokes are provided at both end portions of the inner yoke. Permanent magnets are provided on inner sides of the outer yokes and on outer sides of the inner yoke with polarities thereof which face opposite surfaces of the outer yoke. The inner yoke is made opposite to each other or with polarities thereof which face only the outer yokes being made opposite each other to thereby a field. An armature made up of a bobbin of non-magnetic and insulating materials is provided. A coil is provided around the bobbin between the permanent magnets via air gaps in such a manner as to move in an axial direction or in such a manner that. The coil is wound around the bobbin. A case is constructed on an exterior of the bobbin. A coil portion is made watertight. A fluid supply port and a fluid discharge port are provided on the bobbin or the case. A cooling fluid is caused to flow between the coil and the case so that the coil is cooled directly.

摘要翻译： 具有冷却功能的音圈式线性电机。 一个形成为θ形的闭合磁路，由设置在与纵向中心轴线平行布置的磁性材料构成的一对外轭铁之间的内磁轭，以与所述一对外磁轭平行 。 外轭铁和侧轭架设置在内轭铁的两端部。 永磁体设置在外磁轭的内侧，内侧磁轭的外侧具有与外磁轭相对的面的极性。 内轭铁彼此相对或者具有仅具有彼此相对的外轭铁的极性，从而形成场。 提供由非磁性和绝缘材料的线轴构成的电枢。 通过气隙以永久磁铁的方式在轴向上或以这样一种方式移动的方式在线圈之间设置线圈。 线圈缠绕在线轴上。 在筒管的外部构造壳体。 线圈部分防水。 流体供给口和流体排出口设置在筒管或壳体上。 使冷却流体在线圈和壳体之间流动，使得线圈被直接冷却。

公开(公告)号：US09033071B2

公开(公告)日：2015-05-19

申请号：US13990915

申请日：2012-09-05

申请人： Mitsuhiro Koga ,  Naoki Tsujimoto

发明人： Mitsuhiro Koga ,  Naoki Tsujimoto

IPC分类号： E02F9/08 ,  F01N3/00

CPC分类号： E02F9/0858 ,  E02F9/0833 ,  E02F9/0866 ,  F01N3/00

摘要： A hydraulic excavator is provided with a lower traveling unit, an upper structure, an engine, a hydraulic pump, an engine compartment, a pump compartment and a plurality of filter devices. The upper structure is rotatably disposed on the lower traveling unit. The pump compartment provided on the upper structure for housing the hydraulic pump. The pump compartment has a door that allows access to an interior of the pump compartment. The filter devices, which are disposed adjacent to each other, are disposed at positions that are mutually offset in a height direction of the hydraulic excavator.

摘要翻译： 液压挖掘机具有下行进单元，上结构，发动机，液压泵，发动机舱，泵室和多个过滤装置。 上部结构可旋转地设置在下行进单元上。 泵室设置在上部结构上，用于容纳液压泵。 泵室具有允许进入泵室内部的门。 相邻配置的过滤装置配置在液压挖掘机的高度方向上相互偏移的位置。

公开(公告)号：US20050206246A1

公开(公告)日：2005-09-22

申请号：US10516689

申请日：2003-06-05

申请人： Haruki Yahara ,  Makoto Matsumoto ,  Mitsuhiro Koga ,  Mitsuhiro Matsuzaki

发明人： Haruki Yahara ,  Makoto Matsumoto ,  Mitsuhiro Koga ,  Mitsuhiro Matsuzaki

IPC分类号： H02K33/18 ,  H02K41/035 ,  H02K41/00

CPC分类号： H02K41/0356

摘要： A small vacuum chamber is provided which needs no load lock chamber. In a voice coil type linear motor including a closed magnetic circuit formed into the θ-shape, by a pair of outer yokes (11), an inner yoke (12) and side yokes (13) and in which an armature is fixed to an inner side of the outer yoke (11), whereas permanent magnet sides are allowed to move, a coil (18) is wound around a bobbin (17), an exterior case 23 for the bobbin is constructed so as to make a coil portion watertight, and a fluid supply port and a fluid discharge port are provided either on the bobbin or on the case, whereby a cooling fluid is made to flow between the coil and the case so as to cool the coil directly.

摘要翻译： 提供一个小型真空室，无需负载锁定室。 在包括通过一对外轭铁（11），内磁轭（12）和侧轭铁（13）形成为θ形的闭合磁路的音圈型线性电动机中，其中电枢固定到 外磁轭（11）的内侧，而永磁体侧允许移动，线圈（18）缠绕在线轴（17）上，线轴的外壳23被构造成使线圈部分水密 并且在筒管或壳体上设置流体供给口和流体排出口，由此使冷却流体在线圈和壳体之间流动，从而直接冷却线圈。