公开(公告)号：US06689668B1

公开(公告)日：2004-02-10

申请号：US09652650

申请日：2000-08-31

申请人： Mohamed el-Hamdi ,  Tony T. Phan ,  Luther Hendrix ,  Bradley T. Moore

发明人： Mohamed el-Hamdi ,  Tony T. Phan ,  Luther Hendrix ,  Bradley T. Moore

IPC分类号： H01L2120

CPC分类号： H01L28/84 ,  H01L27/10852

摘要： Various methods are provided of forming capacitor electrodes for integrated circuit memory cells in which out-diffusion of dopant from doped silicon layers is controlled by deposition of barrier layers, such as layers of undoped silicon and/or oxide. In one aspect, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first barrier layer on the doped silicon layer. A hemispherical grain polysilicon source layer is formed on the first barrier layer and a hemispherical grain silicon layer on the hemispherical grain polysilicon source layer. By controlling out-diffusion of dopant, HSG grain size, density and uniformity, as well as DRAM memory cell capacitance, may be enhanced, while at the same time maintaining reactor throughput.

摘要翻译： 提供了形成用于集成电路存储单元的电容器电极的各种方法，其中通过沉积阻挡层（例如未掺杂的硅和/或氧化物层）来控制来自掺杂硅层的掺杂剂的外扩散。 一方面，提供一种在衬底上形成半球形晶粒硅的方法，其包括在衬底上形成第一掺杂硅层和在掺杂硅层上形成第一势垒层。 半球形晶粒多晶硅源层形成在半球形晶粒多晶硅源层上的第一势垒层和半球状晶粒硅层上。 通过控制掺杂剂的扩散，可以提高HSG晶粒尺寸，密度和均匀性以及DRAM存储单元电容，同时保持反应器的生产量。

公开(公告)号：US08639561B2

公开(公告)日：2014-01-28

申请号：US13222349

申请日：2011-08-31

申请人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore ,  Clinton W. Wright

发明人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore ,  Clinton W. Wright

IPC分类号： G06Q10/00 ,  G06Q30/00 ,  G06F17/00 ,  G06G7/00

CPC分类号： G06Q10/063

摘要： Embodiments include a computer system, method and program product for managing a software program installed on a computer hardware system, the software program subject to a software license. A retrieval of data is performed in which the data indicates actual usage of the software program and the computer hardware system, and processor power of the computer hardware system. In addition, a retrieval of licensing data from the software license is performed in which the licensing data indicates a permitted number of or fee for installations of the software program and a permitted amount of or fee for processor power of the computer hardware system in which the software program is installed. Whether to decommission a copy of the software program based on the data indicating actual usage, the licensing data, a projected amount of future usage of the software program, and criticality of the software program is determined and reported.

摘要翻译： 实施例包括用于管理安装在计算机硬件系统上的软件程序的计算机系统，方法和程序产品，该软件程序受软件许可证管理。 执行数据的检索，其中数据指示软件程序和计算机硬件系统的实际使用以及计算机硬件系统的处理器能力。 此外，执行从软件许可证检索许可数据，其中许可数据指示软件程序的安装的允许数量或费用，以及计算机硬件系统的处理器功率的允许量或费用，其中 软件程序已安装。 是否根据指示实际使用的数据停止软件程序的副本，确定并报告许可数据，软件程序的预计未来使用量以及软件程序的关键性。

公开(公告)号：US06552776B1

公开(公告)日：2003-04-22

申请号：US09183176

申请日：1998-10-30

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

IPC分类号： G03B2754

CPC分类号： G03F7/70558 ,  G03F7/70191 ,  G03F7/706

摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

公开(公告)号：US6060345A

公开(公告)日：2000-05-09

申请号：US844924

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823814

摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

摘要翻译： 公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。 该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层， 栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中 作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中 。 有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域 具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

公开(公告)号：US5962894A

公开(公告)日：1999-10-05

申请号：US30052

申请日：1998-02-24

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/41775 ,  H01L29/66621 ,  H01L29/78

摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.

摘要翻译： 公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间​​的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极 在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。 形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散 在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体， 覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。 有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

公开(公告)号：US5930634A

公开(公告)日：1999-07-27

申请号：US844927

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/28035 ,  H01L21/28052 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.

摘要翻译： 公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层 第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料 作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极 活跃区域。 有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

公开(公告)号：US5877058A

公开(公告)日：1999-03-02

申请号：US703272

申请日：1996-08-26

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L29/6656

摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。

公开(公告)号：US5710054A

公开(公告)日：1998-01-20

申请号：US703273

申请日：1996-08-26

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265 ,  H01L21/385

CPC分类号： H01L29/66575 ,  H01L21/2256 ,  H01L21/2257 ,  H01L21/28105 ,  H01L21/28114 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： A method of forming a shallow junction in an IGFET is disclosed. The method includes forming a gate insulator on a semiconductor substrate of first conductivity type, forming a gate electrode on the gate insulator, forming a sidewall insulator on an edge of the gate electrode, forming a silicon-based spacer over the substrate such that the sidewall insulator separates and electrically isolates the spacer and the gate electrode, and diffusing a dopant of second conductivity type from the spacer into the substrate. The diffused dopant forms a shallow region of second conductivity type in the substrate, and a shallow junction is substantially laterally aligned with the edge of the gate electrode.

摘要翻译： 公开了一种在IGFET中形成浅结的方法。 该方法包括在第一导电类型的半导体衬底上形成栅极绝缘体，在栅极绝缘体上形成栅电极，在栅电极的边缘上形成侧壁绝缘体，在衬底上形成硅基间隔物，使得侧壁 绝缘体分离并电隔离间隔物和栅电极，并将第二导电类型的掺杂剂从间隔物扩散到衬底中。 扩散掺杂剂在衬底中形成第二导电类型的浅区域，并且浅结与栅电极的边缘基本上横向对齐。

公开(公告)号：US5384272A

公开(公告)日：1995-01-24

申请号：US266744

申请日：1994-06-28

申请人： Effiong E. Ibok ,  Bradley T. Moore

发明人： Effiong E. Ibok ,  Bradley T. Moore

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/266

CPC分类号： H01L29/66825 ,  H01L27/115

摘要： The invention provides a method for manufacturing a non-volatile, virtual ground memory element. The method includes the steps of depositing a first polysilicon layer on gate oxide on a silicon substrate, depositing or growing a first oxide layer, depositing a barrier nitride layer and patterning the first polysilicon layer, the first oxide layer and the barrier nitride layer to form a floating gate. The method further includes the steps of doping a region of the silicon substrate adjacent the floating gate to form a bit line region and oxidizing the bit line region in a wet ambient. The method further includes the use of a spacer nitride or spacer oxide/nitride layer to protect the edge of the floating gate during oxidation and to reduce dopant diffusion under the gate. The method further includes the steps of stripping the barrier nitride layer, depositing a second polysilicon layer and patterning the second polysilicon layer to form a control gate.

摘要翻译： 本发明提供一种用于制造非易失性虚拟地面存储元件的方法。 该方法包括以下步骤：在硅衬底上的栅极氧化物上沉积第一多晶硅层，沉积或生长第一氧化物层，沉积势垒氮化物层和图案化第一多晶硅层，第一氧化物层和势垒氮化物层以形成 一个浮动门。 该方法还包括以下步骤：在与浮置栅极相邻的硅衬底的区域中掺杂以形成位线区域并在湿环境中氧化位线区域。 该方法还包括使用间隔氮化物或间隔氧化物/氮化物层来在氧化期间保护浮置栅极的边缘并且减少栅极下方的掺杂剂扩散。 该方法还包括剥离势垒氮化物层，沉积第二多晶硅层和图案化第二多晶硅层以形成控制栅极的步骤。

公开(公告)号：US09230273B2

公开(公告)日：2016-01-05

申请号：US12845420

申请日：2010-07-28

申请人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore

发明人： Michael K. Boudreau ,  Jamie B. Marsnik ,  Bradley T. Moore

IPC分类号： G06Q10/10 ,  G06Q40/02 ,  G06Q30/04 ,  G06Q30/06 ,  G06Q40/00

CPC分类号： G06Q30/06 ,  G06Q30/0603 ,  G06Q30/0607 ,  G06Q40/12

摘要： The new creation and use of entitlement constraint templates methods and systems can be linked to software offerings in a software catalog. Allowing software catalog experts to link contractual entitlement data with software product offerings via constraint templates on such a varying list of constraint types, establishes a highly robust software catalog knowledge base. The result is significant cost savings in terms of time spent inputting entitlement constraint data by contract analysts as well as minimizing errors by those analysts who would otherwise be required to have a very high level of expertise in the software offerings while potentially inputting the same constraint data repeated times.

摘要翻译： 授权约束模板方法和系统的新创建和使用可以链接到软件目录中的软件产品。 允许软件目录专家通过约束模板通过约束类型的变化列表将合同授权数据与软件产品产品相关联，建立了高度可靠的软件目录知识库。 结果是在合同分析师输入授权约束数据所花费的时间方面节省了大量成本，同时也减少了那些在软件产品中具有非常高水平专业知识的分析师的错误，同时潜在地输入相同的约束数据 重复次数。